diff options
| author | 2014-04-26 01:47:52 -0400 | |
|---|---|---|
| committer | 2014-04-26 01:47:52 -0400 | |
| commit | a272803dcb5fdd6b0b5181cbdeff9ad68c9db934 (patch) | |
| tree | fb3adb5aa75e57b87b4c5e1176e96600d68cfe25 /src | |
| parent | added (fake) physical addresses for where to put framebuffer in VRAM (diff) | |
| download | yuzu-a272803dcb5fdd6b0b5181cbdeff9ad68c9db934.tar.gz yuzu-a272803dcb5fdd6b0b5181cbdeff9ad68c9db934.tar.xz yuzu-a272803dcb5fdd6b0b5181cbdeff9ad68c9db934.zip | |
added preliminary DataSynchronizationBarrier support with simple DMA copy
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/hle/mrc.cpp | 46 |
1 files changed, 39 insertions, 7 deletions
diff --git a/src/core/hle/mrc.cpp b/src/core/hle/mrc.cpp index 04d6cb5a5..5223be7c9 100644 --- a/src/core/hle/mrc.cpp +++ b/src/core/hle/mrc.cpp | |||
| @@ -1,10 +1,43 @@ | |||
| 1 | #include "mrc.h" | 1 | // Copyright 2014 Citra Emulator Project |
| 2 | #include "hle.h" | 2 | // Licensed under GPLv2 |
| 3 | // Refer to the license.txt file included. | ||
| 4 | |||
| 5 | #include "core/hle/mrc.h" | ||
| 6 | #include "core/hle/hle.h" | ||
| 7 | #include "core/mem_map.h" | ||
| 8 | #include "core/core.h" | ||
| 3 | 9 | ||
| 4 | namespace HLE { | 10 | namespace HLE { |
| 5 | 11 | ||
| 12 | enum { | ||
| 13 | CMD_GX_REQUEST_DMA = 0x00000000, | ||
| 14 | }; | ||
| 15 | |||
| 16 | /// Data synchronization barrier | ||
| 17 | u32 DataSynchronizationBarrier(u32* command_buffer) { | ||
| 18 | u32 command = command_buffer[0]; | ||
| 19 | |||
| 20 | switch (command) { | ||
| 21 | |||
| 22 | case CMD_GX_REQUEST_DMA: | ||
| 23 | { | ||
| 24 | u32* src = (u32*)Memory::GetPointer(command_buffer[1]); | ||
| 25 | u32* dst = (u32*)Memory::GetPointer(command_buffer[2]); | ||
| 26 | u32 size = command_buffer[3]; | ||
| 27 | memcpy(dst, src, size); | ||
| 28 | } | ||
| 29 | break; | ||
| 30 | |||
| 31 | default: | ||
| 32 | ERROR_LOG(OSHLE, "MRC::DataSynchronizationBarrier unknown command 0x%08X", command); | ||
| 33 | return -1; | ||
| 34 | } | ||
| 35 | |||
| 36 | return 0; | ||
| 37 | } | ||
| 38 | |||
| 6 | /// Returns the coprocessor (in this case, syscore) command buffer pointer | 39 | /// Returns the coprocessor (in this case, syscore) command buffer pointer |
| 7 | Addr CallGetThreadCommandBuffer() { | 40 | Addr GetThreadCommandBuffer() { |
| 8 | // Called on insruction: mrc p15, 0, r0, c13, c0, 3 | 41 | // Called on insruction: mrc p15, 0, r0, c13, c0, 3 |
| 9 | // Returns an address in OSHLE memory for the CPU to read/write to | 42 | // Returns an address in OSHLE memory for the CPU to read/write to |
| 10 | RETURN(CMD_BUFFER_ADDR); | 43 | RETURN(CMD_BUFFER_ADDR); |
| @@ -16,14 +49,13 @@ u32 CallMRC(ARM11_MRC_OPERATION operation) { | |||
| 16 | switch (operation) { | 49 | switch (operation) { |
| 17 | 50 | ||
| 18 | case DATA_SYNCHRONIZATION_BARRIER: | 51 | case DATA_SYNCHRONIZATION_BARRIER: |
| 19 | ERROR_LOG(OSHLE, "Unimplemented MRC operation DATA_SYNCHRONIZATION_BARRIER"); | 52 | return DataSynchronizationBarrier((u32*)Memory::GetPointer(PARAM(0))); |
| 20 | break; | ||
| 21 | 53 | ||
| 22 | case CALL_GET_THREAD_COMMAND_BUFFER: | 54 | case CALL_GET_THREAD_COMMAND_BUFFER: |
| 23 | return CallGetThreadCommandBuffer(); | 55 | return GetThreadCommandBuffer(); |
| 24 | 56 | ||
| 25 | default: | 57 | default: |
| 26 | ERROR_LOG(OSHLE, "Unimplemented MRC operation 0x%02X", operation); | 58 | ERROR_LOG(OSHLE, "unimplemented MRC operation 0x%02X", operation); |
| 27 | break; | 59 | break; |
| 28 | } | 60 | } |
| 29 | return -1; | 61 | return -1; |