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| author | 2019-02-02 23:44:38 -0300 | |
|---|---|---|
| committer | 2019-02-03 00:25:40 -0300 | |
| commit | 9feb68085d05a265fd9ec7f26791390516cd3bd6 (patch) | |
| tree | fff3e69a9b3408596e44dd1abdc2e6a398d6e613 /src | |
| parent | shader_ir/memory: Add LD_L 64 bits loads (diff) | |
| download | yuzu-9feb68085d05a265fd9ec7f26791390516cd3bd6.tar.gz yuzu-9feb68085d05a265fd9ec7f26791390516cd3bd6.tar.xz yuzu-9feb68085d05a265fd9ec7f26791390516cd3bd6.zip | |
shader_bytecode: Rename BytesN enums to BitsN
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 6 | ||||
| -rw-r--r-- | src/video_core/shader/decode/memory.cpp | 8 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 713b01c9f..2f5a966d2 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -217,9 +217,9 @@ enum class StoreType : u64 { | |||
| 217 | Signed8 = 1, | 217 | Signed8 = 1, |
| 218 | Unsigned16 = 2, | 218 | Unsigned16 = 2, |
| 219 | Signed16 = 3, | 219 | Signed16 = 3, |
| 220 | Bytes32 = 4, | 220 | Bits32 = 4, |
| 221 | Bytes64 = 5, | 221 | Bits64 = 5, |
| 222 | Bytes128 = 6, | 222 | Bits128 = 6, |
| 223 | }; | 223 | }; |
| 224 | 224 | ||
| 225 | enum class IMinMaxExchange : u64 { | 225 | enum class IMinMaxExchange : u64 { |
diff --git a/src/video_core/shader/decode/memory.cpp b/src/video_core/shader/decode/memory.cpp index 63965525c..2321a37a2 100644 --- a/src/video_core/shader/decode/memory.cpp +++ b/src/video_core/shader/decode/memory.cpp | |||
| @@ -115,10 +115,10 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, const BasicBlock& code, u32 pc) { | |||
| 115 | }; | 115 | }; |
| 116 | 116 | ||
| 117 | switch (instr.ldst_sl.type.Value()) { | 117 | switch (instr.ldst_sl.type.Value()) { |
| 118 | case Tegra::Shader::StoreType::Bytes32: | 118 | case Tegra::Shader::StoreType::Bits32: |
| 119 | SetRegister(bb, instr.gpr0, GetLmem(0)); | 119 | SetRegister(bb, instr.gpr0, GetLmem(0)); |
| 120 | break; | 120 | break; |
| 121 | case Tegra::Shader::StoreType::Bytes64: { | 121 | case Tegra::Shader::StoreType::Bits64: { |
| 122 | SetTemporal(bb, 0, GetLmem(0)); | 122 | SetTemporal(bb, 0, GetLmem(0)); |
| 123 | SetTemporal(bb, 1, GetLmem(4)); | 123 | SetTemporal(bb, 1, GetLmem(4)); |
| 124 | SetRegister(bb, instr.gpr0, GetTemporal(0)); | 124 | SetRegister(bb, instr.gpr0, GetTemporal(0)); |
| @@ -127,7 +127,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, const BasicBlock& code, u32 pc) { | |||
| 127 | } | 127 | } |
| 128 | default: | 128 | default: |
| 129 | UNIMPLEMENTED_MSG("LD_L Unhandled type: {}", | 129 | UNIMPLEMENTED_MSG("LD_L Unhandled type: {}", |
| 130 | static_cast<unsigned>(instr.ldst_sl.type.Value())); | 130 | static_cast<u32>(instr.ldst_sl.type.Value())); |
| 131 | } | 131 | } |
| 132 | break; | 132 | break; |
| 133 | } | 133 | } |
| @@ -217,7 +217,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, const BasicBlock& code, u32 pc) { | |||
| 217 | Immediate(static_cast<s32>(instr.smem_imm))); | 217 | Immediate(static_cast<s32>(instr.smem_imm))); |
| 218 | 218 | ||
| 219 | switch (instr.ldst_sl.type.Value()) { | 219 | switch (instr.ldst_sl.type.Value()) { |
| 220 | case Tegra::Shader::StoreType::Bytes32: | 220 | case Tegra::Shader::StoreType::Bits32: |
| 221 | SetLocalMemory(bb, index, GetRegister(instr.gpr0)); | 221 | SetLocalMemory(bb, index, GetRegister(instr.gpr0)); |
| 222 | break; | 222 | break; |
| 223 | default: | 223 | default: |