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| author |  Lioncash | 2014-12-28 12:13:13 -0500 |
|---|---|---|
| committer | Lioncash | 2014-12-28 12:13:13 -0500 |
| commit | 9f5b53f9ff616d7df3b8ea3709963831f4e96f42 (patch) | |
| tree | 332a9b37c12e1fd6e9066ae0880b990182277dc7 /src | |
| parent | armemu: Simplify USAT16/UXTB/UXTAB (diff) | |
| download | yuzu-9f5b53f9ff616d7df3b8ea3709963831f4e96f42.tar.gz yuzu-9f5b53f9ff616d7df3b8ea3709963831f4e96f42.tar.xz yuzu-9f5b53f9ff616d7df3b8ea3709963831f4e96f42.zip | |
armemu: Simplify REV/REV16/SXTH/SXTAH
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/interpreter/armemu.cpp | 64 |
1 files changed, 26 insertions, 38 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index dcc0acafe..1b3a3478d 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp | |||
| @@ -6350,51 +6350,39 @@ L_stm_s_takeabort: | |||
| 6350 | 6350 | ||
| 6351 | return 1; | 6351 | return 1; |
| 6352 | } | 6352 | } |
| 6353 | case 0x6b: | ||
| 6354 | { | ||
| 6355 | ARMword Rm; | ||
| 6356 | int ror = -1; | ||
| 6357 | 6353 | ||
| 6358 | switch (BITS(4, 11)) { | 6354 | case 0x6b: // REV, REV16, SXTH, and SXTAH |
| 6359 | case 0x07: | 6355 | { |
| 6360 | ror = 0; | 6356 | const u8 op2 = BITS(5, 7); |
| 6361 | break; | ||
| 6362 | case 0x47: | ||
| 6363 | ror = 8; | ||
| 6364 | break; | ||
| 6365 | case 0x87: | ||
| 6366 | ror = 16; | ||
| 6367 | break; | ||
| 6368 | case 0xc7: | ||
| 6369 | ror = 24; | ||
| 6370 | break; | ||
| 6371 | 6357 | ||
| 6372 | case 0xf3: // REV | 6358 | // REV |
| 6373 | DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24); | 6359 | if (op2 == 0x01) { |
| 6374 | return 1; | 6360 | DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24); |
| 6375 | case 0xfb: // REV16 | 6361 | return 1; |
| 6376 | DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8); | ||
| 6377 | return 1; | ||
| 6378 | default: | ||
| 6379 | break; | ||
| 6380 | } | 6362 | } |
| 6363 | // REV16 | ||
| 6364 | else if (op2 == 0x05) { | ||
| 6365 | DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8); | ||
| 6366 | return 1; | ||
| 6367 | } | ||
| 6368 | else if (op2 == 0x03) { | ||
| 6369 | const u8 rotate = BITS(10, 11) * 8; | ||
| 6381 | 6370 | ||
| 6382 | if (ror == -1) | 6371 | u32 rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFFFF) & 0xFFFF); |
| 6383 | break; | 6372 | if (rm & 0x8000) |
| 6384 | 6373 | rm |= 0xffff0000; | |
| 6385 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF); | ||
| 6386 | if (Rm & 0x8000) | ||
| 6387 | Rm |= 0xffff0000; | ||
| 6388 | 6374 | ||
| 6389 | if (BITS(16, 19) == 0xf) | 6375 | // SXTH, otherwise SXTAH |
| 6390 | /* SXTH */ | 6376 | if (BITS(16, 19) == 15) |
| 6391 | state->Reg[BITS(12, 15)] = Rm; | 6377 | state->Reg[BITS(12, 15)] = rm; |
| 6392 | else | 6378 | else |
| 6393 | /* SXTAH */ | 6379 | state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm; |
| 6394 | state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm; | ||
| 6395 | 6380 | ||
| 6396 | return 1; | 6381 | return 1; |
| 6382 | } | ||
| 6397 | } | 6383 | } |
| 6384 | break; | ||
| 6385 | |||
| 6398 | case 0x6c: // UXTB16 and UXTAB16 | 6386 | case 0x6c: // UXTB16 and UXTAB16 |
| 6399 | { | 6387 | { |
| 6400 | const u8 rm_idx = BITS(0, 3); | 6388 | const u8 rm_idx = BITS(0, 3); |