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authorGravatar bunnei2018-04-21 11:16:21 -0400
committerGravatar bunnei2018-04-24 17:40:43 -0400
commit9e11a76e926a7190880063d8fc8c3d97003b9938 (patch)
tree13d1749f110f5517ef506e10f575693ea2aa63ca /src
parentMerge pull request #386 from Subv/gpu_query (diff)
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memory_manager: Use GPUVAdddr, not PAddr, for GPU addresses.
Diffstat (limited to 'src')
-rw-r--r--src/video_core/command_processor.cpp4
-rw-r--r--src/video_core/engines/maxwell_3d.cpp11
-rw-r--r--src/video_core/memory_manager.cpp72
-rw-r--r--src/video_core/memory_manager.h16
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer.cpp6
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer_cache.cpp4
-rw-r--r--src/yuzu/debugger/graphics/graphics_surface.cpp4
7 files changed, 57 insertions, 60 deletions
diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index d4cdb4ab2..7850ae103 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -90,9 +90,7 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
90} 90}
91 91
92void GPU::ProcessCommandList(GPUVAddr address, u32 size) { 92void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
93 // TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an 93 const VAddr head_address = memory_manager->GpuToCpuAddress(address);
94 // application VAddr.
95 const VAddr head_address = memory_manager->PhysicalToVirtualAddress(address);
96 VAddr current_addr = head_address; 94 VAddr current_addr = head_address;
97 while (current_addr < head_address + size * sizeof(CommandHeader)) { 95 while (current_addr < head_address + size * sizeof(CommandHeader)) {
98 const CommandHeader header = {Memory::Read32(current_addr)}; 96 const CommandHeader header = {Memory::Read32(current_addr)};
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 35773a695..8d7d627b8 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -145,7 +145,7 @@ void Maxwell3D::ProcessQueryGet() {
145 GPUVAddr sequence_address = regs.query.QueryAddress(); 145 GPUVAddr sequence_address = regs.query.QueryAddress();
146 // Since the sequence address is given as a GPU VAddr, we have to convert it to an application 146 // Since the sequence address is given as a GPU VAddr, we have to convert it to an application
147 // VAddr before writing. 147 // VAddr before writing.
148 VAddr address = memory_manager.PhysicalToVirtualAddress(sequence_address); 148 VAddr address = memory_manager.GpuToCpuAddress(sequence_address);
149 149
150 // TODO(Subv): Support the other query units. 150 // TODO(Subv): Support the other query units.
151 ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop, 151 ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
@@ -225,8 +225,7 @@ void Maxwell3D::ProcessCBData(u32 value) {
225 // Don't allow writing past the end of the buffer. 225 // Don't allow writing past the end of the buffer.
226 ASSERT(regs.const_buffer.cb_pos + sizeof(u32) <= regs.const_buffer.cb_size); 226 ASSERT(regs.const_buffer.cb_pos + sizeof(u32) <= regs.const_buffer.cb_size);
227 227
228 VAddr address = 228 VAddr address = memory_manager.GpuToCpuAddress(buffer_address + regs.const_buffer.cb_pos);
229 memory_manager.PhysicalToVirtualAddress(buffer_address + regs.const_buffer.cb_pos);
230 229
231 Memory::Write32(address, value); 230 Memory::Write32(address, value);
232 231
@@ -238,7 +237,7 @@ Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
238 GPUVAddr tic_base_address = regs.tic.TICAddress(); 237 GPUVAddr tic_base_address = regs.tic.TICAddress();
239 238
240 GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry); 239 GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry);
241 VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu); 240 VAddr tic_address_cpu = memory_manager.GpuToCpuAddress(tic_address_gpu);
242 241
243 Texture::TICEntry tic_entry; 242 Texture::TICEntry tic_entry;
244 Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry)); 243 Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
@@ -268,7 +267,7 @@ Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const {
268 GPUVAddr tsc_base_address = regs.tsc.TSCAddress(); 267 GPUVAddr tsc_base_address = regs.tsc.TSCAddress();
269 268
270 GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry); 269 GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry);
271 VAddr tsc_address_cpu = memory_manager.PhysicalToVirtualAddress(tsc_address_gpu); 270 VAddr tsc_address_cpu = memory_manager.GpuToCpuAddress(tsc_address_gpu);
272 271
273 Texture::TSCEntry tsc_entry; 272 Texture::TSCEntry tsc_entry;
274 Memory::ReadBlock(tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry)); 273 Memory::ReadBlock(tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry));
@@ -293,7 +292,7 @@ std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderSt
293 current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) { 292 current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) {
294 293
295 Texture::TextureHandle tex_handle{ 294 Texture::TextureHandle tex_handle{
296 Memory::Read32(memory_manager.PhysicalToVirtualAddress(current_texture))}; 295 Memory::Read32(memory_manager.GpuToCpuAddress(current_texture))};
297 296
298 Texture::FullTextureInfo tex_info{}; 297 Texture::FullTextureInfo tex_info{};
299 // TODO(Subv): Use the shader to determine which textures are actually accessed. 298 // TODO(Subv): Use the shader to determine which textures are actually accessed.
diff --git a/src/video_core/memory_manager.cpp b/src/video_core/memory_manager.cpp
index 2e1edee03..3f21071c0 100644
--- a/src/video_core/memory_manager.cpp
+++ b/src/video_core/memory_manager.cpp
@@ -8,90 +8,90 @@
8 8
9namespace Tegra { 9namespace Tegra {
10 10
11PAddr MemoryManager::AllocateSpace(u64 size, u64 align) { 11GPUVAddr MemoryManager::AllocateSpace(u64 size, u64 align) {
12 boost::optional<PAddr> paddr = FindFreeBlock(size, align); 12 boost::optional<GPUVAddr> gpu_addr = FindFreeBlock(size, align);
13 ASSERT(paddr); 13 ASSERT(gpu_addr);
14 14
15 for (u64 offset = 0; offset < size; offset += PAGE_SIZE) { 15 for (u64 offset = 0; offset < size; offset += PAGE_SIZE) {
16 ASSERT(PageSlot(*paddr + offset) == static_cast<u64>(PageStatus::Unmapped)); 16 ASSERT(PageSlot(*gpu_addr + offset) == static_cast<u64>(PageStatus::Unmapped));
17 PageSlot(*paddr + offset) = static_cast<u64>(PageStatus::Allocated); 17 PageSlot(*gpu_addr + offset) = static_cast<u64>(PageStatus::Allocated);
18 } 18 }
19 19
20 return *paddr; 20 return *gpu_addr;
21} 21}
22 22
23PAddr MemoryManager::AllocateSpace(PAddr paddr, u64 size, u64 align) { 23GPUVAddr MemoryManager::AllocateSpace(GPUVAddr gpu_addr, u64 size, u64 align) {
24 for (u64 offset = 0; offset < size; offset += PAGE_SIZE) { 24 for (u64 offset = 0; offset < size; offset += PAGE_SIZE) {
25 ASSERT(PageSlot(paddr + offset) == static_cast<u64>(PageStatus::Unmapped)); 25 ASSERT(PageSlot(gpu_addr + offset) == static_cast<u64>(PageStatus::Unmapped));
26 PageSlot(paddr + offset) = static_cast<u64>(PageStatus::Allocated); 26 PageSlot(gpu_addr + offset) = static_cast<u64>(PageStatus::Allocated);
27 } 27 }
28 28
29 return paddr; 29 return gpu_addr;
30} 30}
31 31
32PAddr MemoryManager::MapBufferEx(VAddr vaddr, u64 size) { 32GPUVAddr MemoryManager::MapBufferEx(VAddr cpu_addr, u64 size) {
33 boost::optional<PAddr> paddr = FindFreeBlock(size, PAGE_SIZE); 33 boost::optional<GPUVAddr> gpu_addr = FindFreeBlock(size, PAGE_SIZE);
34 ASSERT(paddr); 34 ASSERT(gpu_addr);
35 35
36 for (u64 offset = 0; offset < size; offset += PAGE_SIZE) { 36 for (u64 offset = 0; offset < size; offset += PAGE_SIZE) {
37 ASSERT(PageSlot(*paddr + offset) == static_cast<u64>(PageStatus::Unmapped)); 37 ASSERT(PageSlot(*gpu_addr + offset) == static_cast<u64>(PageStatus::Unmapped));
38 PageSlot(*paddr + offset) = vaddr + offset; 38 PageSlot(*gpu_addr + offset) = cpu_addr + offset;
39 } 39 }
40 40
41 return *paddr; 41 return *gpu_addr;
42} 42}
43 43
44PAddr MemoryManager::MapBufferEx(VAddr vaddr, PAddr paddr, u64 size) { 44GPUVAddr MemoryManager::MapBufferEx(VAddr cpu_addr, GPUVAddr gpu_addr, u64 size) {
45 ASSERT((paddr & PAGE_MASK) == 0); 45 ASSERT((gpu_addr & PAGE_MASK) == 0);
46 46
47 for (u64 offset = 0; offset < size; offset += PAGE_SIZE) { 47 for (u64 offset = 0; offset < size; offset += PAGE_SIZE) {
48 ASSERT(PageSlot(paddr + offset) == static_cast<u64>(PageStatus::Allocated)); 48 ASSERT(PageSlot(gpu_addr + offset) == static_cast<u64>(PageStatus::Allocated));
49 PageSlot(paddr + offset) = vaddr + offset; 49 PageSlot(gpu_addr + offset) = cpu_addr + offset;
50 } 50 }
51 51
52 return paddr; 52 return gpu_addr;
53} 53}
54 54
55boost::optional<PAddr> MemoryManager::FindFreeBlock(u64 size, u64 align) { 55boost::optional<GPUVAddr> MemoryManager::FindFreeBlock(u64 size, u64 align) {
56 PAddr paddr = 0; 56 GPUVAddr gpu_addr = 0;
57 u64 free_space = 0; 57 u64 free_space = 0;
58 align = (align + PAGE_MASK) & ~PAGE_MASK; 58 align = (align + PAGE_MASK) & ~PAGE_MASK;
59 59
60 while (paddr + free_space < MAX_ADDRESS) { 60 while (gpu_addr + free_space < MAX_ADDRESS) {
61 if (!IsPageMapped(paddr + free_space)) { 61 if (!IsPageMapped(gpu_addr + free_space)) {
62 free_space += PAGE_SIZE; 62 free_space += PAGE_SIZE;
63 if (free_space >= size) { 63 if (free_space >= size) {
64 return paddr; 64 return gpu_addr;
65 } 65 }
66 } else { 66 } else {
67 paddr += free_space + PAGE_SIZE; 67 gpu_addr += free_space + PAGE_SIZE;
68 free_space = 0; 68 free_space = 0;
69 paddr = Common::AlignUp(paddr, align); 69 gpu_addr = Common::AlignUp(gpu_addr, align);
70 } 70 }
71 } 71 }
72 72
73 return {}; 73 return {};
74} 74}
75 75
76VAddr MemoryManager::PhysicalToVirtualAddress(PAddr paddr) { 76VAddr MemoryManager::GpuToCpuAddress(GPUVAddr gpu_addr) {
77 VAddr base_addr = PageSlot(paddr); 77 VAddr base_addr = PageSlot(gpu_addr);
78 ASSERT(base_addr != static_cast<u64>(PageStatus::Unmapped)); 78 ASSERT(base_addr != static_cast<u64>(PageStatus::Unmapped));
79 return base_addr + (paddr & PAGE_MASK); 79 return base_addr + (gpu_addr & PAGE_MASK);
80} 80}
81 81
82bool MemoryManager::IsPageMapped(PAddr paddr) { 82bool MemoryManager::IsPageMapped(GPUVAddr gpu_addr) {
83 return PageSlot(paddr) != static_cast<u64>(PageStatus::Unmapped); 83 return PageSlot(gpu_addr) != static_cast<u64>(PageStatus::Unmapped);
84} 84}
85 85
86VAddr& MemoryManager::PageSlot(PAddr paddr) { 86VAddr& MemoryManager::PageSlot(GPUVAddr gpu_addr) {
87 auto& block = page_table[(paddr >> (PAGE_BITS + PAGE_TABLE_BITS)) & PAGE_TABLE_MASK]; 87 auto& block = page_table[(gpu_addr >> (PAGE_BITS + PAGE_TABLE_BITS)) & PAGE_TABLE_MASK];
88 if (!block) { 88 if (!block) {
89 block = std::make_unique<PageBlock>(); 89 block = std::make_unique<PageBlock>();
90 for (unsigned index = 0; index < PAGE_BLOCK_SIZE; index++) { 90 for (unsigned index = 0; index < PAGE_BLOCK_SIZE; index++) {
91 (*block)[index] = static_cast<u64>(PageStatus::Unmapped); 91 (*block)[index] = static_cast<u64>(PageStatus::Unmapped);
92 } 92 }
93 } 93 }
94 return (*block)[(paddr >> PAGE_BITS) & PAGE_BLOCK_MASK]; 94 return (*block)[(gpu_addr >> PAGE_BITS) & PAGE_BLOCK_MASK];
95} 95}
96 96
97} // namespace Tegra 97} // namespace Tegra
diff --git a/src/video_core/memory_manager.h b/src/video_core/memory_manager.h
index b73e283f8..4710cb21f 100644
--- a/src/video_core/memory_manager.h
+++ b/src/video_core/memory_manager.h
@@ -18,20 +18,20 @@ class MemoryManager final {
18public: 18public:
19 MemoryManager() = default; 19 MemoryManager() = default;
20 20
21 PAddr AllocateSpace(u64 size, u64 align); 21 GPUVAddr AllocateSpace(u64 size, u64 align);
22 PAddr AllocateSpace(PAddr paddr, u64 size, u64 align); 22 GPUVAddr AllocateSpace(GPUVAddr gpu_addr, u64 size, u64 align);
23 PAddr MapBufferEx(VAddr vaddr, u64 size); 23 GPUVAddr MapBufferEx(VAddr cpu_addr, u64 size);
24 PAddr MapBufferEx(VAddr vaddr, PAddr paddr, u64 size); 24 GPUVAddr MapBufferEx(VAddr cpu_addr, GPUVAddr gpu_addr, u64 size);
25 VAddr PhysicalToVirtualAddress(PAddr paddr); 25 VAddr GpuToCpuAddress(GPUVAddr gpu_addr);
26 26
27 static constexpr u64 PAGE_BITS = 16; 27 static constexpr u64 PAGE_BITS = 16;
28 static constexpr u64 PAGE_SIZE = 1 << PAGE_BITS; 28 static constexpr u64 PAGE_SIZE = 1 << PAGE_BITS;
29 static constexpr u64 PAGE_MASK = PAGE_SIZE - 1; 29 static constexpr u64 PAGE_MASK = PAGE_SIZE - 1;
30 30
31private: 31private:
32 boost::optional<PAddr> FindFreeBlock(u64 size, u64 align = 1); 32 boost::optional<GPUVAddr> FindFreeBlock(u64 size, u64 align = 1);
33 bool IsPageMapped(PAddr paddr); 33 bool IsPageMapped(GPUVAddr gpu_addr);
34 VAddr& PageSlot(PAddr paddr); 34 VAddr& PageSlot(GPUVAddr gpu_addr);
35 35
36 enum class PageStatus : u64 { 36 enum class PageStatus : u64 {
37 Unmapped = 0xFFFFFFFFFFFFFFFFULL, 37 Unmapped = 0xFFFFFFFFFFFFFFFFULL,
diff --git a/src/video_core/renderer_opengl/gl_rasterizer.cpp b/src/video_core/renderer_opengl/gl_rasterizer.cpp
index 82001e7b4..8568d6762 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer.cpp
@@ -233,7 +233,7 @@ void RasterizerOpenGL::SetupShaders(u8* buffer_ptr, GLintptr buffer_offset) {
233 // Fetch program code from memory 233 // Fetch program code from memory
234 GLShader::ProgramCode program_code; 234 GLShader::ProgramCode program_code;
235 const u64 gpu_address{gpu.regs.code_address.CodeAddress() + shader_config.offset}; 235 const u64 gpu_address{gpu.regs.code_address.CodeAddress() + shader_config.offset};
236 const VAddr cpu_address{gpu.memory_manager.PhysicalToVirtualAddress(gpu_address)}; 236 const VAddr cpu_address{gpu.memory_manager.GpuToCpuAddress(gpu_address)};
237 Memory::ReadBlock(cpu_address, program_code.data(), program_code.size() * sizeof(u64)); 237 Memory::ReadBlock(cpu_address, program_code.data(), program_code.size() * sizeof(u64));
238 GLShader::ShaderSetup setup{std::move(program_code)}; 238 GLShader::ShaderSetup setup{std::move(program_code)};
239 239
@@ -395,7 +395,7 @@ void RasterizerOpenGL::DrawArrays() {
395 if (is_indexed) { 395 if (is_indexed) {
396 const auto& memory_manager = Core::System().GetInstance().GPU().memory_manager; 396 const auto& memory_manager = Core::System().GetInstance().GPU().memory_manager;
397 const VAddr index_data_addr{ 397 const VAddr index_data_addr{
398 memory_manager->PhysicalToVirtualAddress(regs.index_array.StartAddress())}; 398 memory_manager->GpuToCpuAddress(regs.index_array.StartAddress())};
399 Memory::ReadBlock(index_data_addr, offseted_buffer, index_buffer_size); 399 Memory::ReadBlock(index_data_addr, offseted_buffer, index_buffer_size);
400 400
401 index_buffer_offset = buffer_offset; 401 index_buffer_offset = buffer_offset;
@@ -659,7 +659,7 @@ u32 RasterizerOpenGL::SetupConstBuffers(Maxwell::ShaderStage stage, GLuint progr
659 buffer_draw_state.enabled = true; 659 buffer_draw_state.enabled = true;
660 buffer_draw_state.bindpoint = current_bindpoint + bindpoint; 660 buffer_draw_state.bindpoint = current_bindpoint + bindpoint;
661 661
662 VAddr addr = gpu.memory_manager->PhysicalToVirtualAddress(buffer.address); 662 VAddr addr = gpu.memory_manager->GpuToCpuAddress(buffer.address);
663 std::vector<u8> data(used_buffer.GetSize() * sizeof(float)); 663 std::vector<u8> data(used_buffer.GetSize() * sizeof(float));
664 Memory::ReadBlock(addr, data.data(), data.size()); 664 Memory::ReadBlock(addr, data.data(), data.size());
665 665
diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
index 7410471cc..46f0f25aa 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
@@ -1028,7 +1028,7 @@ Surface RasterizerCacheOpenGL::GetTextureSurface(const Tegra::Texture::FullTextu
1028 auto& gpu = Core::System::GetInstance().GPU(); 1028 auto& gpu = Core::System::GetInstance().GPU();
1029 1029
1030 SurfaceParams params; 1030 SurfaceParams params;
1031 params.addr = gpu.memory_manager->PhysicalToVirtualAddress(config.tic.Address()); 1031 params.addr = gpu.memory_manager->GpuToCpuAddress(config.tic.Address());
1032 params.width = config.tic.Width(); 1032 params.width = config.tic.Width();
1033 params.height = config.tic.Height(); 1033 params.height = config.tic.Height();
1034 params.is_tiled = config.tic.IsTiled(); 1034 params.is_tiled = config.tic.IsTiled();
@@ -1106,7 +1106,7 @@ SurfaceSurfaceRect_Tuple RasterizerCacheOpenGL::GetFramebufferSurfaces(
1106 color_params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight; 1106 color_params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
1107 SurfaceParams depth_params = color_params; 1107 SurfaceParams depth_params = color_params;
1108 1108
1109 color_params.addr = memory_manager->PhysicalToVirtualAddress(config.Address()); 1109 color_params.addr = memory_manager->GpuToCpuAddress(config.Address());
1110 color_params.pixel_format = SurfaceParams::PixelFormatFromRenderTargetFormat(config.format); 1110 color_params.pixel_format = SurfaceParams::PixelFormatFromRenderTargetFormat(config.format);
1111 color_params.component_type = SurfaceParams::ComponentTypeFromRenderTarget(config.format); 1111 color_params.component_type = SurfaceParams::ComponentTypeFromRenderTarget(config.format);
1112 color_params.UpdateParams(); 1112 color_params.UpdateParams();
diff --git a/src/yuzu/debugger/graphics/graphics_surface.cpp b/src/yuzu/debugger/graphics/graphics_surface.cpp
index 5fada74be..5cadb807e 100644
--- a/src/yuzu/debugger/graphics/graphics_surface.cpp
+++ b/src/yuzu/debugger/graphics/graphics_surface.cpp
@@ -378,7 +378,7 @@ void GraphicsSurfaceWidget::OnUpdate() {
378 // TODO: Implement a good way to visualize alpha components! 378 // TODO: Implement a good way to visualize alpha components!
379 379
380 QImage decoded_image(surface_width, surface_height, QImage::Format_ARGB32); 380 QImage decoded_image(surface_width, surface_height, QImage::Format_ARGB32);
381 VAddr address = gpu.memory_manager->PhysicalToVirtualAddress(surface_address); 381 VAddr address = gpu.memory_manager->GpuToCpuAddress(surface_address);
382 382
383 auto unswizzled_data = 383 auto unswizzled_data =
384 Tegra::Texture::UnswizzleTexture(address, surface_format, surface_width, surface_height); 384 Tegra::Texture::UnswizzleTexture(address, surface_format, surface_width, surface_height);
@@ -437,7 +437,7 @@ void GraphicsSurfaceWidget::SaveSurface() {
437 pixmap->save(&file, "PNG"); 437 pixmap->save(&file, "PNG");
438 } else if (selectedFilter == bin_filter) { 438 } else if (selectedFilter == bin_filter) {
439 auto& gpu = Core::System::GetInstance().GPU(); 439 auto& gpu = Core::System::GetInstance().GPU();
440 VAddr address = gpu.memory_manager->PhysicalToVirtualAddress(surface_address); 440 VAddr address = gpu.memory_manager->GpuToCpuAddress(surface_address);
441 441
442 const u8* buffer = Memory::GetPointer(address); 442 const u8* buffer = Memory::GetPointer(address);
443 ASSERT_MSG(buffer != nullptr, "Memory not accessible"); 443 ASSERT_MSG(buffer != nullptr, "Memory not accessible");