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| author |  Lioncash | 2018-09-17 19:25:53 -0400 |
|---|---|---|
| committer | Lioncash | 2018-09-17 19:25:55 -0400 |
| commit | 9a8dbba1e59fb9d8cbd2c394802b18eb7dc9330d (patch) | |
| tree | 0043fc7841b1e729eb78e6e37ed90bb65bba1044 /src | |
| parent | Merge pull request #1311 from FernandoS27/fast-swizzle (diff) | |
| download | yuzu-9a8dbba1e59fb9d8cbd2c394802b18eb7dc9330d.tar.gz yuzu-9a8dbba1e59fb9d8cbd2c394802b18eb7dc9330d.tar.xz yuzu-9a8dbba1e59fb9d8cbd2c394802b18eb7dc9330d.zip | |
gl_shader_decompiler: Avoid truncation warnings within LD_A and ST_A code
These are internally stored as u64 values, so using u32 here causes
truncation warnings. Instead, we can just use u64 and preserve the bit
width.
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 252ff18fc..4e7d4a24e 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -1779,8 +1779,8 @@ private: | |||
| 1779 | Tegra::Shader::IpaMode input_mode{Tegra::Shader::IpaInterpMode::Perspective, | 1779 | Tegra::Shader::IpaMode input_mode{Tegra::Shader::IpaInterpMode::Perspective, |
| 1780 | Tegra::Shader::IpaSampleMode::Default}; | 1780 | Tegra::Shader::IpaSampleMode::Default}; |
| 1781 | 1781 | ||
| 1782 | u32 next_element = instr.attribute.fmt20.element; | 1782 | u64 next_element = instr.attribute.fmt20.element; |
| 1783 | u32 next_index = static_cast<u32>(instr.attribute.fmt20.index.Value()); | 1783 | u64 next_index = static_cast<u64>(instr.attribute.fmt20.index.Value()); |
| 1784 | 1784 | ||
| 1785 | const auto LoadNextElement = [&](u32 reg_offset) { | 1785 | const auto LoadNextElement = [&](u32 reg_offset) { |
| 1786 | regs.SetRegisterToInputAttibute(instr.gpr0.Value() + reg_offset, next_element, | 1786 | regs.SetRegisterToInputAttibute(instr.gpr0.Value() + reg_offset, next_element, |
| @@ -1844,8 +1844,8 @@ private: | |||
| 1844 | ASSERT_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) == 0, | 1844 | ASSERT_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) == 0, |
| 1845 | "Unaligned attribute loads are not supported"); | 1845 | "Unaligned attribute loads are not supported"); |
| 1846 | 1846 | ||
| 1847 | u32 next_element = instr.attribute.fmt20.element; | 1847 | u64 next_element = instr.attribute.fmt20.element; |
| 1848 | u32 next_index = static_cast<u32>(instr.attribute.fmt20.index.Value()); | 1848 | u64 next_index = static_cast<u64>(instr.attribute.fmt20.index.Value()); |
| 1849 | 1849 | ||
| 1850 | const auto StoreNextElement = [&](u32 reg_offset) { | 1850 | const auto StoreNextElement = [&](u32 reg_offset) { |
| 1851 | regs.SetOutputAttributeToRegister(static_cast<Attribute::Index>(next_index), | 1851 | regs.SetOutputAttributeToRegister(static_cast<Attribute::Index>(next_index), |