diff options
| author | 2020-12-30 23:38:49 -0800 | |
|---|---|---|
| committer | 2021-01-28 21:42:25 -0800 | |
| commit | 9a4e148f9e27671f58f0d32afb2c9a85adc136c5 (patch) | |
| tree | 71ef149bbc52000e53e3be90c15629538a18f82f /src | |
| parent | core: hle: kernel: Rename Thread to KThread. (diff) | |
| download | yuzu-9a4e148f9e27671f58f0d32afb2c9a85adc136c5.tar.gz yuzu-9a4e148f9e27671f58f0d32afb2c9a85adc136c5.tar.xz yuzu-9a4e148f9e27671f58f0d32afb2c9a85adc136c5.zip | |
arm: arm_dynarmic: Skip calls when JIT is invalid.
- This can happen if called from an idle or suspension thread.
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_32.cpp | 12 | ||||
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_64.cpp | 12 |
2 files changed, 24 insertions, 0 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp index 6c4c8e9e4..7d7e191ea 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp | |||
| @@ -251,10 +251,16 @@ void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) { | |||
| 251 | } | 251 | } |
| 252 | 252 | ||
| 253 | void ARM_Dynarmic_32::ChangeProcessorID(std::size_t new_core_id) { | 253 | void ARM_Dynarmic_32::ChangeProcessorID(std::size_t new_core_id) { |
| 254 | if (!jit) { | ||
| 255 | return; | ||
| 256 | } | ||
| 254 | jit->ChangeProcessorID(new_core_id); | 257 | jit->ChangeProcessorID(new_core_id); |
| 255 | } | 258 | } |
| 256 | 259 | ||
| 257 | void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) { | 260 | void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) { |
| 261 | if (!jit) { | ||
| 262 | return; | ||
| 263 | } | ||
| 258 | Dynarmic::A32::Context context; | 264 | Dynarmic::A32::Context context; |
| 259 | jit->SaveContext(context); | 265 | jit->SaveContext(context); |
| 260 | ctx.cpu_registers = context.Regs(); | 266 | ctx.cpu_registers = context.Regs(); |
| @@ -264,6 +270,9 @@ void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) { | |||
| 264 | } | 270 | } |
| 265 | 271 | ||
| 266 | void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { | 272 | void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { |
| 273 | if (!jit) { | ||
| 274 | return; | ||
| 275 | } | ||
| 267 | Dynarmic::A32::Context context; | 276 | Dynarmic::A32::Context context; |
| 268 | context.Regs() = ctx.cpu_registers; | 277 | context.Regs() = ctx.cpu_registers; |
| 269 | context.ExtRegs() = ctx.extension_registers; | 278 | context.ExtRegs() = ctx.extension_registers; |
| @@ -273,6 +282,9 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { | |||
| 273 | } | 282 | } |
| 274 | 283 | ||
| 275 | void ARM_Dynarmic_32::PrepareReschedule() { | 284 | void ARM_Dynarmic_32::PrepareReschedule() { |
| 285 | if (!jit) { | ||
| 286 | return; | ||
| 287 | } | ||
| 276 | jit->HaltExecution(); | 288 | jit->HaltExecution(); |
| 277 | } | 289 | } |
| 278 | 290 | ||
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp index 4c5ebca22..f755a39cf 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp | |||
| @@ -290,10 +290,16 @@ void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) { | |||
| 290 | } | 290 | } |
| 291 | 291 | ||
| 292 | void ARM_Dynarmic_64::ChangeProcessorID(std::size_t new_core_id) { | 292 | void ARM_Dynarmic_64::ChangeProcessorID(std::size_t new_core_id) { |
| 293 | if (!jit) { | ||
| 294 | return; | ||
| 295 | } | ||
| 293 | jit->ChangeProcessorID(new_core_id); | 296 | jit->ChangeProcessorID(new_core_id); |
| 294 | } | 297 | } |
| 295 | 298 | ||
| 296 | void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) { | 299 | void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) { |
| 300 | if (!jit) { | ||
| 301 | return; | ||
| 302 | } | ||
| 297 | ctx.cpu_registers = jit->GetRegisters(); | 303 | ctx.cpu_registers = jit->GetRegisters(); |
| 298 | ctx.sp = jit->GetSP(); | 304 | ctx.sp = jit->GetSP(); |
| 299 | ctx.pc = jit->GetPC(); | 305 | ctx.pc = jit->GetPC(); |
| @@ -305,6 +311,9 @@ void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) { | |||
| 305 | } | 311 | } |
| 306 | 312 | ||
| 307 | void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) { | 313 | void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) { |
| 314 | if (!jit) { | ||
| 315 | return; | ||
| 316 | } | ||
| 308 | jit->SetRegisters(ctx.cpu_registers); | 317 | jit->SetRegisters(ctx.cpu_registers); |
| 309 | jit->SetSP(ctx.sp); | 318 | jit->SetSP(ctx.sp); |
| 310 | jit->SetPC(ctx.pc); | 319 | jit->SetPC(ctx.pc); |
| @@ -316,6 +325,9 @@ void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) { | |||
| 316 | } | 325 | } |
| 317 | 326 | ||
| 318 | void ARM_Dynarmic_64::PrepareReschedule() { | 327 | void ARM_Dynarmic_64::PrepareReschedule() { |
| 328 | if (!jit) { | ||
| 329 | return; | ||
| 330 | } | ||
| 319 | jit->HaltExecution(); | 331 | jit->HaltExecution(); |
| 320 | } | 332 | } |
| 321 | 333 | ||