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authorGravatar Yuri Kunde Schlesner2015-07-16 19:15:33 -0700
committerGravatar Yuri Kunde Schlesner2015-07-16 19:15:33 -0700
commit8932b23dccffa0e2c46006f26335ce7113d13a29 (patch)
tree408be8e40c7edacb9447d59c743e0ad99108d096 /src
parentRemove webchat link from readme (diff)
parentarm_dyncom_interpreter: Simplify assignment in SMLAW (diff)
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Merge pull request #935 from lioncash/smlaw
arm_dyncom_interpreter: Simplify assignment in SMLAW
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index b00eb49a9..34cfb8cb2 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -5695,7 +5695,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
5695 const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF); 5695 const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF);
5696 const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16); 5696 const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16);
5697 5697
5698 RD = (result & (0xFFFFFFFFFFFFFFFFLL >> 15)) >> 16; 5698 RD = BITS(result, 16, 47);
5699 5699
5700 if ((result >> 16) != (s32)RD) 5700 if ((result >> 16) != (s32)RD)
5701 cpu->Cpsr |= (1 << 27); 5701 cpu->Cpsr |= (1 << 27);