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authorGravatar Lioncash2015-05-22 23:14:22 -0400
committerGravatar Lioncash2015-05-22 23:14:22 -0400
commit86179384413099c1950b9077e95ccc9056238e28 (patch)
tree39a48f706498b56b44724945b013bcb3aeb83807 /src
parentMerge pull request #801 from purpasmart96/hid_stubs (diff)
downloadyuzu-86179384413099c1950b9077e95ccc9056238e28.tar.gz
yuzu-86179384413099c1950b9077e95ccc9056238e28.tar.xz
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dyncom: Remove unnecessary parameter for load/store operations
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp78
1 files changed, 39 insertions, 39 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 890f8a86b..84b24a160 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -284,7 +284,7 @@ static unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sh
284 return shifter_operand; 284 return shifter_operand;
285} 285}
286 286
287typedef void (*get_addr_fp_t)(ARMul_State *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw); 287typedef void (*get_addr_fp_t)(ARMul_State *cpu, unsigned int inst, unsigned int &virt_addr);
288 288
289struct ldst_inst { 289struct ldst_inst {
290 unsigned int inst; 290 unsigned int inst;
@@ -302,7 +302,7 @@ struct ldst_inst {
302#define P_BIT BIT(inst, 24) 302#define P_BIT BIT(inst, 24)
303#define OFFSET_12 BITS(inst, 0, 11) 303#define OFFSET_12 BITS(inst, 0, 11)
304 304
305static void LnSWoUB(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 305static void LnSWoUB(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
306 unsigned int Rn = BITS(inst, 16, 19); 306 unsigned int Rn = BITS(inst, 16, 19);
307 unsigned int addr; 307 unsigned int addr;
308 308
@@ -314,7 +314,7 @@ static void LnSWoUB(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsign
314 virt_addr = addr; 314 virt_addr = addr;
315} 315}
316 316
317static void LnSWoUB(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 317static void LnSWoUB(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
318 unsigned int Rn = BITS(inst, 16, 19); 318 unsigned int Rn = BITS(inst, 16, 19);
319 unsigned int Rm = BITS(inst, 0, 3); 319 unsigned int Rm = BITS(inst, 0, 3);
320 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 320 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
@@ -329,7 +329,7 @@ static void LnSWoUB(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigne
329 virt_addr = addr; 329 virt_addr = addr;
330} 330}
331 331
332static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 332static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
333 unsigned int Rn = BITS(inst, 16, 19); 333 unsigned int Rn = BITS(inst, 16, 19);
334 unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn); 334 unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn);
335 335
@@ -341,7 +341,7 @@ static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, u
341 virt_addr = addr; 341 virt_addr = addr;
342} 342}
343 343
344static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 344static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
345 unsigned int Rn = BITS(inst, 16, 19); 345 unsigned int Rn = BITS(inst, 16, 19);
346 unsigned int addr; 346 unsigned int addr;
347 347
@@ -356,7 +356,7 @@ static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, un
356 cpu->Reg[Rn] = addr; 356 cpu->Reg[Rn] = addr;
357} 357}
358 358
359static void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 359static void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
360 unsigned int addr; 360 unsigned int addr;
361 unsigned int Rn = BITS(inst, 16, 19); 361 unsigned int Rn = BITS(inst, 16, 19);
362 unsigned int Rm = BITS(inst, 0, 3); 362 unsigned int Rm = BITS(inst, 0, 3);
@@ -374,7 +374,7 @@ static void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsign
374 cpu->Reg[Rn] = addr; 374 cpu->Reg[Rn] = addr;
375} 375}
376 376
377static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 377static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
378 unsigned int Rn = BITS(inst, 16, 19); 378 unsigned int Rn = BITS(inst, 16, 19);
379 unsigned int Rm = BITS(inst, 0, 3); 379 unsigned int Rm = BITS(inst, 0, 3);
380 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 380 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
@@ -393,7 +393,7 @@ static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, uns
393 } 393 }
394} 394}
395 395
396static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 396static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
397 unsigned int shift = BITS(inst, 5, 6); 397 unsigned int shift = BITS(inst, 5, 6);
398 unsigned int shift_imm = BITS(inst, 7, 11); 398 unsigned int shift_imm = BITS(inst, 7, 11);
399 unsigned int Rn = BITS(inst, 16, 19); 399 unsigned int Rn = BITS(inst, 16, 19);
@@ -444,7 +444,7 @@ static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int ins
444 cpu->Reg[Rn] = addr; 444 cpu->Reg[Rn] = addr;
445} 445}
446 446
447static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 447static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
448 unsigned int shift = BITS(inst, 5, 6); 448 unsigned int shift = BITS(inst, 5, 6);
449 unsigned int shift_imm = BITS(inst, 7, 11); 449 unsigned int shift_imm = BITS(inst, 7, 11);
450 unsigned int Rn = BITS(inst, 16, 19); 450 unsigned int Rn = BITS(inst, 16, 19);
@@ -493,7 +493,7 @@ static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int in
493 } 493 }
494} 494}
495 495
496static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 496static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
497 unsigned int Rn = BITS(inst, 16, 19); 497 unsigned int Rn = BITS(inst, 16, 19);
498 unsigned int Rm = BITS(inst, 0, 3); 498 unsigned int Rm = BITS(inst, 0, 3);
499 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 499 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
@@ -509,7 +509,7 @@ static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, un
509 } 509 }
510} 510}
511 511
512static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 512static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
513 unsigned int immedL = BITS(inst, 0, 3); 513 unsigned int immedL = BITS(inst, 0, 3);
514 unsigned int immedH = BITS(inst, 8, 11); 514 unsigned int immedH = BITS(inst, 8, 11);
515 unsigned int Rn = BITS(inst, 16, 19); 515 unsigned int Rn = BITS(inst, 16, 19);
@@ -525,7 +525,7 @@ static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned
525 virt_addr = addr; 525 virt_addr = addr;
526} 526}
527 527
528static void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 528static void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
529 unsigned int addr; 529 unsigned int addr;
530 unsigned int Rn = BITS(inst, 16, 19); 530 unsigned int Rn = BITS(inst, 16, 19);
531 unsigned int Rm = BITS(inst, 0, 3); 531 unsigned int Rm = BITS(inst, 0, 3);
@@ -540,7 +540,7 @@ static void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned i
540 virt_addr = addr; 540 virt_addr = addr;
541} 541}
542 542
543static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 543static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
544 unsigned int Rn = BITS(inst, 16, 19); 544 unsigned int Rn = BITS(inst, 16, 19);
545 unsigned int immedH = BITS(inst, 8, 11); 545 unsigned int immedH = BITS(inst, 8, 11);
546 unsigned int immedL = BITS(inst, 0, 3); 546 unsigned int immedL = BITS(inst, 0, 3);
@@ -559,7 +559,7 @@ static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsig
559 cpu->Reg[Rn] = addr; 559 cpu->Reg[Rn] = addr;
560} 560}
561 561
562static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 562static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
563 unsigned int Rn = BITS(inst, 16, 19); 563 unsigned int Rn = BITS(inst, 16, 19);
564 unsigned int immedH = BITS(inst, 8, 11); 564 unsigned int immedH = BITS(inst, 8, 11);
565 unsigned int immedL = BITS(inst, 0, 3); 565 unsigned int immedL = BITS(inst, 0, 3);
@@ -578,7 +578,7 @@ static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsi
578 } 578 }
579} 579}
580 580
581static void MLnS(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 581static void MLnS(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
582 unsigned int Rn = BITS(inst, 16, 19); 582 unsigned int Rn = BITS(inst, 16, 19);
583 unsigned int Rm = BITS(inst, 0, 3); 583 unsigned int Rm = BITS(inst, 0, 3);
584 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 584 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
@@ -593,7 +593,7 @@ static void MLnS(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsig
593 } 593 }
594} 594}
595 595
596static void LdnStM(DecrementBefore)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 596static void LdnStM(DecrementBefore)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
597 unsigned int Rn = BITS(inst, 16, 19); 597 unsigned int Rn = BITS(inst, 16, 19);
598 unsigned int i = BITS(inst, 0, 15); 598 unsigned int i = BITS(inst, 0, 15);
599 int count = 0; 599 int count = 0;
@@ -609,7 +609,7 @@ static void LdnStM(DecrementBefore)(ARMul_State* cpu, unsigned int inst, unsigne
609 cpu->Reg[Rn] -= count * 4; 609 cpu->Reg[Rn] -= count * 4;
610} 610}
611 611
612static void LdnStM(IncrementBefore)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 612static void LdnStM(IncrementBefore)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
613 unsigned int Rn = BITS(inst, 16, 19); 613 unsigned int Rn = BITS(inst, 16, 19);
614 unsigned int i = BITS(inst, 0, 15); 614 unsigned int i = BITS(inst, 0, 15);
615 int count = 0; 615 int count = 0;
@@ -625,7 +625,7 @@ static void LdnStM(IncrementBefore)(ARMul_State* cpu, unsigned int inst, unsigne
625 cpu->Reg[Rn] += count * 4; 625 cpu->Reg[Rn] += count * 4;
626} 626}
627 627
628static void LdnStM(IncrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 628static void LdnStM(IncrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
629 unsigned int Rn = BITS(inst, 16, 19); 629 unsigned int Rn = BITS(inst, 16, 19);
630 unsigned int i = BITS(inst, 0, 15); 630 unsigned int i = BITS(inst, 0, 15);
631 int count = 0; 631 int count = 0;
@@ -641,7 +641,7 @@ static void LdnStM(IncrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned
641 cpu->Reg[Rn] += count * 4; 641 cpu->Reg[Rn] += count * 4;
642} 642}
643 643
644static void LdnStM(DecrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 644static void LdnStM(DecrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
645 unsigned int Rn = BITS(inst, 16, 19); 645 unsigned int Rn = BITS(inst, 16, 19);
646 unsigned int i = BITS(inst, 0, 15); 646 unsigned int i = BITS(inst, 0, 15);
647 int count = 0; 647 int count = 0;
@@ -659,7 +659,7 @@ static void LdnStM(DecrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned
659 } 659 }
660} 660}
661 661
662static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { 662static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
663 unsigned int shift = BITS(inst, 5, 6); 663 unsigned int shift = BITS(inst, 5, 6);
664 unsigned int shift_imm = BITS(inst, 7, 11); 664 unsigned int shift_imm = BITS(inst, 7, 11);
665 unsigned int Rn = BITS(inst, 16, 19); 665 unsigned int Rn = BITS(inst, 16, 19);
@@ -4460,7 +4460,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4460 { 4460 {
4461 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 4461 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
4462 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4462 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4463 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); 4463 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4464 4464
4465 unsigned int inst = inst_cream->inst; 4465 unsigned int inst = inst_cream->inst;
4466 if (BIT(inst, 22) && !BIT(inst, 15)) { 4466 if (BIT(inst, 22) && !BIT(inst, 15)) {
@@ -4549,7 +4549,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4549 LDR_INST: 4549 LDR_INST:
4550 { 4550 {
4551 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4551 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4552 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); 4552 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4553 4553
4554 unsigned int value = ReadMemory32(cpu, addr); 4554 unsigned int value = ReadMemory32(cpu, addr);
4555 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4555 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
@@ -4571,7 +4571,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4571 { 4571 {
4572 if (CondPassed(cpu, inst_base->cond)) { 4572 if (CondPassed(cpu, inst_base->cond)) {
4573 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4573 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4574 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); 4574 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4575 4575
4576 unsigned int value = ReadMemory32(cpu, addr); 4576 unsigned int value = ReadMemory32(cpu, addr);
4577 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4577 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
@@ -4617,7 +4617,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4617 { 4617 {
4618 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 4618 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
4619 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4619 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4620 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); 4620 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4621 4621
4622 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr); 4622 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr);
4623 4623
@@ -4635,7 +4635,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4635 { 4635 {
4636 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 4636 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
4637 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4637 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4638 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); 4638 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4639 4639
4640 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr); 4640 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr);
4641 4641
@@ -4654,7 +4654,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4654 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 4654 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
4655 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4655 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4656 // Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0) 4656 // Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0)
4657 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); 4657 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4658 4658
4659 // The 3DS doesn't have LPAE (Large Physical Access Extension), so it 4659 // The 3DS doesn't have LPAE (Large Physical Access Extension), so it
4660 // wouldn't do this as a single read. 4660 // wouldn't do this as a single read.
@@ -4755,7 +4755,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4755 { 4755 {
4756 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 4756 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
4757 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4757 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4758 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); 4758 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4759 4759
4760 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = ReadMemory16(cpu, addr); 4760 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = ReadMemory16(cpu, addr);
4761 if (BITS(inst_cream->inst, 12, 15) == 15) { 4761 if (BITS(inst_cream->inst, 12, 15) == 15) {
@@ -4772,7 +4772,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4772 { 4772 {
4773 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 4773 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
4774 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4774 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4775 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); 4775 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4776 unsigned int value = Memory::Read8(addr); 4776 unsigned int value = Memory::Read8(addr);
4777 if (BIT(value, 7)) { 4777 if (BIT(value, 7)) {
4778 value |= 0xffffff00; 4778 value |= 0xffffff00;
@@ -4792,7 +4792,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4792 { 4792 {
4793 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 4793 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
4794 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4794 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4795 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); 4795 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4796 4796
4797 unsigned int value = ReadMemory16(cpu, addr); 4797 unsigned int value = ReadMemory16(cpu, addr);
4798 if (BIT(value, 15)) { 4798 if (BIT(value, 15)) {
@@ -4813,7 +4813,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4813 { 4813 {
4814 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 4814 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
4815 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4815 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4816 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); 4816 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4817 4817
4818 unsigned int value = ReadMemory32(cpu, addr); 4818 unsigned int value = ReadMemory32(cpu, addr);
4819 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4819 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
@@ -5316,7 +5316,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
5316 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; 5316 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
5317 5317
5318 u32 address = 0; 5318 u32 address = 0;
5319 inst_cream->get_addr(cpu, inst_cream->inst, address, 1); 5319 inst_cream->get_addr(cpu, inst_cream->inst, address);
5320 5320
5321 cpu->Cpsr = ReadMemory32(cpu, address); 5321 cpu->Cpsr = ReadMemory32(cpu, address);
5322 cpu->Reg[15] = ReadMemory32(cpu, address + 4); 5322 cpu->Reg[15] = ReadMemory32(cpu, address + 4);
@@ -5984,7 +5984,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
5984 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; 5984 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
5985 5985
5986 u32 address = 0; 5986 u32 address = 0;
5987 inst_cream->get_addr(cpu, inst_cream->inst, address, 1); 5987 inst_cream->get_addr(cpu, inst_cream->inst, address);
5988 5988
5989 WriteMemory32(cpu, address + 0, cpu->Reg[14]); 5989 WriteMemory32(cpu, address + 0, cpu->Reg[14]);
5990 WriteMemory32(cpu, address + 4, cpu->Spsr_copy); 5990 WriteMemory32(cpu, address + 4, cpu->Spsr_copy);
@@ -6068,7 +6068,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6068 unsigned int Rn = BITS(inst, 16, 19); 6068 unsigned int Rn = BITS(inst, 16, 19);
6069 unsigned int old_RN = cpu->Reg[Rn]; 6069 unsigned int old_RN = cpu->Reg[Rn];
6070 6070
6071 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); 6071 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6072 if (BIT(inst_cream->inst, 22) == 1) { 6072 if (BIT(inst_cream->inst, 22) == 1) {
6073 for (int i = 0; i < 13; i++) { 6073 for (int i = 0; i < 13; i++) {
6074 if (BIT(inst_cream->inst, i)) { 6074 if (BIT(inst_cream->inst, i)) {
@@ -6139,7 +6139,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6139 { 6139 {
6140 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 6140 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
6141 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 6141 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
6142 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); 6142 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6143 6143
6144 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; 6144 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
6145 WriteMemory32(cpu, addr, value); 6145 WriteMemory32(cpu, addr, value);
@@ -6177,7 +6177,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6177 { 6177 {
6178 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 6178 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
6179 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 6179 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
6180 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); 6180 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6181 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; 6181 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
6182 Memory::Write8(addr, value); 6182 Memory::Write8(addr, value);
6183 } 6183 }
@@ -6190,7 +6190,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6190 { 6190 {
6191 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 6191 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
6192 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 6192 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
6193 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); 6193 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6194 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; 6194 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
6195 Memory::Write8(addr, value); 6195 Memory::Write8(addr, value);
6196 } 6196 }
@@ -6203,7 +6203,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6203 { 6203 {
6204 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 6204 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
6205 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 6205 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
6206 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); 6206 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6207 6207
6208 // The 3DS doesn't have the Large Physical Access Extension (LPAE) 6208 // The 3DS doesn't have the Large Physical Access Extension (LPAE)
6209 // so STRD wouldn't store these as a single write. 6209 // so STRD wouldn't store these as a single write.
@@ -6317,7 +6317,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6317 { 6317 {
6318 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 6318 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
6319 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 6319 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
6320 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); 6320 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6321 6321
6322 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff; 6322 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff;
6323 WriteMemory16(cpu, addr, value); 6323 WriteMemory16(cpu, addr, value);
@@ -6331,7 +6331,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6331 { 6331 {
6332 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 6332 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
6333 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 6333 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
6334 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); 6334 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6335 6335
6336 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; 6336 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
6337 WriteMemory32(cpu, addr, value); 6337 WriteMemory32(cpu, addr, value);
HIC SVNT DRACONES