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| author | 2015-05-31 05:32:46 -0400 | |
|---|---|---|
| committer | 2015-05-31 21:51:25 -0400 | |
| commit | 85b1dddda12ebe339cfc462845f899546ffabe41 (patch) | |
| tree | 9430ae8fad554140f7943d2d97c2dc9f297bd0b4 /src | |
| parent | arm_dyncom_thumb: Implement SXTH, SXTB, UXTH, and UXTB. (diff) | |
| download | yuzu-85b1dddda12ebe339cfc462845f899546ffabe41.tar.gz yuzu-85b1dddda12ebe339cfc462845f899546ffabe41.tar.xz yuzu-85b1dddda12ebe339cfc462845f899546ffabe41.zip | |
arm_dyncom_thumb: Implement CPS and SETEND
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_thumb.cpp | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp index 270d966b2..897bb0460 100644 --- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp +++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp | |||
| @@ -287,6 +287,19 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) { | |||
| 287 | *ainstr = subset[BITS(tinstr, 6, 7)] // base | 287 | *ainstr = subset[BITS(tinstr, 6, 7)] // base |
| 288 | | (BITS(tinstr, 0, 2) << 12) // Rd | 288 | | (BITS(tinstr, 0, 2) << 12) // Rd |
| 289 | | BITS(tinstr, 3, 5); // Rm | 289 | | BITS(tinstr, 3, 5); // Rm |
| 290 | } else if ((tinstr & 0x0F00) == 0x600) { | ||
| 291 | if (BIT(tinstr, 5) == 0) { | ||
| 292 | // SETEND | ||
| 293 | *ainstr = 0xF1010000 // base | ||
| 294 | | (BIT(tinstr, 3) << 9); // endian specifier | ||
| 295 | } else { | ||
| 296 | // CPS | ||
| 297 | *ainstr = 0xF1080000 // base | ||
| 298 | | (BIT(tinstr, 0) << 6) // fiq bit | ||
| 299 | | (BIT(tinstr, 1) << 7) // irq bit | ||
| 300 | | (BIT(tinstr, 2) << 8) // abort bit | ||
| 301 | | (BIT(tinstr, 4) << 18); // enable bit | ||
| 302 | } | ||
| 290 | } else if ((tinstr & 0x0F00) == 0x0a00) { | 303 | } else if ((tinstr & 0x0F00) == 0x0a00) { |
| 291 | static const ARMword subset[3] = { | 304 | static const ARMword subset[3] = { |
| 292 | 0xE6BF0F30, // REV | 305 | 0xE6BF0F30, // REV |