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| author | 2018-12-21 00:11:33 -0300 | |
|---|---|---|
| committer | 2019-01-15 17:54:50 -0300 | |
| commit | 8215ae942c72ec20c2ebebbf8fc5784e3f21bb3c (patch) | |
| tree | 4e5932333ba21201504a9570472804e120e77653 /src | |
| parent | shader_decode: Implement IPA (diff) | |
| download | yuzu-8215ae942c72ec20c2ebebbf8fc5784e3f21bb3c.tar.gz yuzu-8215ae942c72ec20c2ebebbf8fc5784e3f21bb3c.tar.xz yuzu-8215ae942c72ec20c2ebebbf8fc5784e3f21bb3c.zip | |
shader_decode: Partially implement BRA
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/shader/decode/other.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index ffdc77d90..3f058324c 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp | |||
| @@ -11,6 +11,7 @@ namespace VideoCommon::Shader { | |||
| 11 | 11 | ||
| 12 | using Tegra::Shader::Instruction; | 12 | using Tegra::Shader::Instruction; |
| 13 | using Tegra::Shader::OpCode; | 13 | using Tegra::Shader::OpCode; |
| 14 | using Tegra::Shader::ConditionCode; | ||
| 14 | 15 | ||
| 15 | u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { | 16 | u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { |
| 16 | const Instruction instr = {program_code[pc]}; | 17 | const Instruction instr = {program_code[pc]}; |
| @@ -45,6 +46,17 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { | |||
| 45 | } | 46 | } |
| 46 | break; | 47 | break; |
| 47 | } | 48 | } |
| 49 | case OpCode::Id::BRA: { | ||
| 50 | UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0, | ||
| 51 | "BRA with constant buffers are not implemented"); | ||
| 52 | |||
| 53 | const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; | ||
| 54 | UNIMPLEMENTED_IF(cc != Tegra::Shader::ConditionCode::T); | ||
| 55 | |||
| 56 | const u32 target = pc + instr.bra.GetBranchTarget(); | ||
| 57 | bb.push_back(Operation(OperationCode::Bra, Immediate(target))); | ||
| 58 | break; | ||
| 59 | } | ||
| 48 | case OpCode::Id::IPA: { | 60 | case OpCode::Id::IPA: { |
| 49 | const auto& attribute = instr.attribute.fmt28; | 61 | const auto& attribute = instr.attribute.fmt28; |
| 50 | const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(), | 62 | const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(), |