diff options
| author | 2015-07-26 11:39:57 -0400 | |
|---|---|---|
| committer | 2015-07-26 13:21:04 -0400 | |
| commit | 816b1ca776fe9d8ac0e618f82afd8e4b5549d582 (patch) | |
| tree | d9346472d6de028c831248b850b4006b81d2dd64 /src | |
| parent | dyncom: Use ARMul_State as an object (diff) | |
| download | yuzu-816b1ca776fe9d8ac0e618f82afd8e4b5549d582.tar.gz yuzu-816b1ca776fe9d8ac0e618f82afd8e4b5549d582.tar.xz yuzu-816b1ca776fe9d8ac0e618f82afd8e4b5549d582.zip | |
dyncom: Use std::array for register arrays
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom.cpp | 8 | ||||
| -rw-r--r-- | src/core/arm/skyeye_common/armstate.h | 49 |
2 files changed, 29 insertions, 28 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp index 9228a49ab..c665f706f 100644 --- a/src/core/arm/dyncom/arm_dyncom.cpp +++ b/src/core/arm/dyncom/arm_dyncom.cpp | |||
| @@ -82,8 +82,8 @@ void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 e | |||
| 82 | } | 82 | } |
| 83 | 83 | ||
| 84 | void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) { | 84 | void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) { |
| 85 | memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers)); | 85 | memcpy(ctx.cpu_registers, state->Reg.data(), sizeof(ctx.cpu_registers)); |
| 86 | memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers)); | 86 | memcpy(ctx.fpu_registers, state->ExtReg.data(), sizeof(ctx.fpu_registers)); |
| 87 | 87 | ||
| 88 | ctx.sp = state->Reg[13]; | 88 | ctx.sp = state->Reg[13]; |
| 89 | ctx.lr = state->Reg[14]; | 89 | ctx.lr = state->Reg[14]; |
| @@ -95,8 +95,8 @@ void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) { | |||
| 95 | } | 95 | } |
| 96 | 96 | ||
| 97 | void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) { | 97 | void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) { |
| 98 | memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers)); | 98 | memcpy(state->Reg.data(), ctx.cpu_registers, sizeof(ctx.cpu_registers)); |
| 99 | memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers)); | 99 | memcpy(state->ExtReg.data(), ctx.fpu_registers, sizeof(ctx.fpu_registers)); |
| 100 | 100 | ||
| 101 | state->Reg[13] = ctx.sp; | 101 | state->Reg[13] = ctx.sp; |
| 102 | state->Reg[14] = ctx.lr; | 102 | state->Reg[14] = ctx.lr; |
diff --git a/src/core/arm/skyeye_common/armstate.h b/src/core/arm/skyeye_common/armstate.h index 041e65ccc..88c1dab9d 100644 --- a/src/core/arm/skyeye_common/armstate.h +++ b/src/core/arm/skyeye_common/armstate.h | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | 17 | ||
| 18 | #pragma once | 18 | #pragma once |
| 19 | 19 | ||
| 20 | #include <array> | ||
| 20 | #include <unordered_map> | 21 | #include <unordered_map> |
| 21 | 22 | ||
| 22 | #include "common/common_types.h" | 23 | #include "common/common_types.h" |
| @@ -141,7 +142,7 @@ enum { | |||
| 141 | RUN = 3 // Continuous execution | 142 | RUN = 3 // Continuous execution |
| 142 | }; | 143 | }; |
| 143 | 144 | ||
| 144 | #define VFP_REG_NUM 64 | 145 | |
| 145 | struct ARMul_State final | 146 | struct ARMul_State final |
| 146 | { | 147 | { |
| 147 | public: | 148 | public: |
| @@ -177,34 +178,34 @@ public: | |||
| 177 | return TFlag ? 2 : 4; | 178 | return TFlag ? 2 : 4; |
| 178 | } | 179 | } |
| 179 | 180 | ||
| 180 | u32 Emulate; // To start and stop emulation | 181 | std::array<u32, 16> Reg; // The current register file |
| 181 | 182 | std::array<u32, 2> Reg_usr; | |
| 182 | // Order of the following register should not be modified | 183 | std::array<u32, 2> Reg_svc; // R13_SVC R14_SVC |
| 183 | u32 Reg[16]; // The current register file | 184 | std::array<u32, 2> Reg_abort; // R13_ABORT R14_ABORT |
| 184 | u32 Cpsr; // The current PSR | 185 | std::array<u32, 2> Reg_undef; // R13 UNDEF R14 UNDEF |
| 185 | u32 Spsr_copy; | 186 | std::array<u32, 2> Reg_irq; // R13_IRQ R14_IRQ |
| 186 | u32 phys_pc; | 187 | std::array<u32, 7> Reg_firq; // R8---R14 FIRQ |
| 187 | u32 Reg_usr[2]; | 188 | std::array<u32, 7> Spsr; // The exception psr's |
| 188 | u32 Reg_svc[2]; // R13_SVC R14_SVC | 189 | std::array<u32, CP15_REGISTER_COUNT> CP15; |
| 189 | u32 Reg_abort[2]; // R13_ABORT R14_ABORT | ||
| 190 | u32 Reg_undef[2]; // R13 UNDEF R14 UNDEF | ||
| 191 | u32 Reg_irq[2]; // R13_IRQ R14_IRQ | ||
| 192 | u32 Reg_firq[7]; // R8---R14 FIRQ | ||
| 193 | u32 Spsr[7]; // The exception psr's | ||
| 194 | u32 Mode; // The current mode | ||
| 195 | u32 Bank; // The current register bank | ||
| 196 | u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode | ||
| 197 | u32 exclusive_state; | ||
| 198 | u32 exclusive_result; | ||
| 199 | u32 CP15[CP15_REGISTER_COUNT]; | ||
| 200 | 190 | ||
| 201 | // FPSID, FPSCR, and FPEXC | 191 | // FPSID, FPSCR, and FPEXC |
| 202 | u32 VFP[VFP_SYSTEM_REGISTER_COUNT]; | 192 | std::array<u32, VFP_SYSTEM_REGISTER_COUNT> VFP; |
| 193 | |||
| 203 | // VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31). | 194 | // VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31). |
| 204 | // VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31), | 195 | // VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31), |
| 205 | // and only 32 singleword registers are accessible (S0-S31). | 196 | // and only 32 singleword registers are accessible (S0-S31). |
| 206 | u32 ExtReg[VFP_REG_NUM]; | 197 | std::array<u32, 64> ExtReg; |
| 207 | /* ---- End of the ordered registers ---- */ | 198 | |
| 199 | u32 Emulate; // To start and stop emulation | ||
| 200 | u32 Cpsr; // The current PSR | ||
| 201 | u32 Spsr_copy; | ||
| 202 | u32 phys_pc; | ||
| 203 | |||
| 204 | u32 Mode; // The current mode | ||
| 205 | u32 Bank; // The current register bank | ||
| 206 | u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode | ||
| 207 | u32 exclusive_state; | ||
| 208 | u32 exclusive_result; | ||
| 208 | 209 | ||
| 209 | u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed | 210 | u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed |
| 210 | unsigned int shifter_carry_out; | 211 | unsigned int shifter_carry_out; |