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| author | 2018-12-17 17:09:23 -0300 | |
|---|---|---|
| committer | 2019-01-15 17:54:51 -0300 | |
| commit | 80183de8846ccf62631d48451535f9a6a4cb8284 (patch) | |
| tree | 5638dffc94d78eb26fffbff72bdef4272b1f52d1 /src | |
| parent | shader_decode: Implement ISET (diff) | |
| download | yuzu-80183de8846ccf62631d48451535f9a6a4cb8284.tar.gz yuzu-80183de8846ccf62631d48451535f9a6a4cb8284.tar.xz yuzu-80183de8846ccf62631d48451535f9a6a4cb8284.zip | |
shader_decode: Implement BFI
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/shader/decode/bfi.cpp | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/src/video_core/shader/decode/bfi.cpp b/src/video_core/shader/decode/bfi.cpp index b94d46ce6..6a851b22e 100644 --- a/src/video_core/shader/decode/bfi.cpp +++ b/src/video_core/shader/decode/bfi.cpp | |||
| @@ -16,7 +16,28 @@ u32 ShaderIR::DecodeBfi(BasicBlock& bb, u32 pc) { | |||
| 16 | const Instruction instr = {program_code[pc]}; | 16 | const Instruction instr = {program_code[pc]}; |
| 17 | const auto opcode = OpCode::Decode(instr); | 17 | const auto opcode = OpCode::Decode(instr); |
| 18 | 18 | ||
| 19 | UNIMPLEMENTED(); | 19 | UNIMPLEMENTED_IF(instr.generates_cc); |
| 20 | |||
| 21 | const auto [base, packed_shift] = [&]() -> std::tuple<Node, Node> { | ||
| 22 | switch (opcode->get().GetId()) { | ||
| 23 | case OpCode::Id::BFI_IMM_R: | ||
| 24 | return {GetRegister(instr.gpr39), Immediate(instr.alu.GetSignedImm20_20())}; | ||
| 25 | default: | ||
| 26 | UNREACHABLE(); | ||
| 27 | } | ||
| 28 | }(); | ||
| 29 | const Node insert = GetRegister(instr.gpr8); | ||
| 30 | |||
| 31 | const Node offset = | ||
| 32 | Operation(OperationCode::UBitwiseAnd, NO_PRECISE, packed_shift, Immediate(0xff)); | ||
| 33 | |||
| 34 | Node bits = | ||
| 35 | Operation(OperationCode::ULogicalShiftRight, NO_PRECISE, packed_shift, Immediate(8)); | ||
| 36 | bits = Operation(OperationCode::UBitwiseAnd, NO_PRECISE, bits, Immediate(0xff)); | ||
| 37 | |||
| 38 | const Node value = | ||
| 39 | Operation(OperationCode::UBitfieldInsert, PRECISE, base, insert, offset, bits); | ||
| 40 | SetRegister(bb, instr.gpr0, value); | ||
| 20 | 41 | ||
| 21 | return pc; | 42 | return pc; |
| 22 | } | 43 | } |