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authorGravatar Lioncash2015-02-04 12:03:43 -0500
committerGravatar Lioncash2015-02-04 13:11:03 -0500
commit7ecedfb970207e5a642aa72b00b54069d2a61f0e (patch)
tree2a6180eddd3a9116d528bfe78362208ec5026556 /src
parentMerge pull request #483 from yuriks/cmake-fix (diff)
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vfp: Throw out unused code
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp_helper.h32
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpinstr.cpp1733
2 files changed, 0 insertions, 1765 deletions
diff --git a/src/core/arm/skyeye_common/vfp/vfp_helper.h b/src/core/arm/skyeye_common/vfp/vfp_helper.h
index dec36c692..af03cb6e7 100644
--- a/src/core/arm/skyeye_common/vfp/vfp_helper.h
+++ b/src/core/arm/skyeye_common/vfp/vfp_helper.h
@@ -102,38 +102,6 @@
102#define FPSCR_C (1 << 29) 102#define FPSCR_C (1 << 29)
103#define FPSCR_V (1 << 28) 103#define FPSCR_V (1 << 28)
104 104
105/* -------------- */
106
107/* From asm/include/vfp.h */
108
109/* FPSCR bits */
110#define FPSCR_DEFAULT_NAN (1<<25)
111#define FPSCR_FLUSHTOZERO (1<<24)
112#define FPSCR_ROUND_NEAREST (0<<22)
113#define FPSCR_ROUND_PLUSINF (1<<22)
114#define FPSCR_ROUND_MINUSINF (2<<22)
115#define FPSCR_ROUND_TOZERO (3<<22)
116#define FPSCR_RMODE_BIT (22)
117#define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
118#define FPSCR_STRIDE_BIT (20)
119#define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
120#define FPSCR_LENGTH_BIT (16)
121#define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
122#define FPSCR_IOE (1<<8)
123#define FPSCR_DZE (1<<9)
124#define FPSCR_OFE (1<<10)
125#define FPSCR_UFE (1<<11)
126#define FPSCR_IXE (1<<12)
127#define FPSCR_IDE (1<<15)
128#define FPSCR_IOC (1<<0)
129#define FPSCR_DZC (1<<1)
130#define FPSCR_OFC (1<<2)
131#define FPSCR_UFC (1<<3)
132#define FPSCR_IXC (1<<4)
133#define FPSCR_IDC (1<<7)
134
135/* ---------------- */
136
137static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift) 105static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
138{ 106{
139 if (shift) { 107 if (shift) {
diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
index 1bdbfec8e..0aa2d5089 100644
--- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
@@ -59,73 +59,6 @@ VMLA_INST:
59} 59}
60#endif 60#endif
61 61
62#ifdef VFP_DYNCOM_TABLE
63DYNCOM_FILL_ACTION(vmla),
64#endif
65#ifdef VFP_DYNCOM_TAG
66int DYNCOM_TAG(vmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
67{
68 int instr_size = INSTR_SIZE;
69 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
70 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
71 return instr_size;
72}
73#endif
74#ifdef VFP_DYNCOM_TRANS
75int DYNCOM_TRANS(vmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
76 //arch_arm_undef(cpu, bb, instr);
77 int m;
78 int n;
79 int d ;
80 int add = (BIT(6) == 0);
81 int s = BIT(8) == 0;
82 Value *mm;
83 Value *nn;
84 Value *tmp;
85 if(s){
86 m = BIT(5) | BITS(0,3) << 1;
87 n = BIT(7) | BITS(16,19) << 1;
88 d = BIT(22) | BITS(12,15) << 1;
89 mm = FR32(m);
90 nn = FR32(n);
91 tmp = FPMUL(nn,mm);
92 if(!add)
93 tmp = FPNEG32(tmp);
94 mm = FR32(d);
95 tmp = FPADD(mm,tmp);
96 //LETS(d,tmp);
97 LETFPS(d,tmp);
98 }else {
99 m = BITS(0,3) | BIT(5) << 4;
100 n = BITS(16,19) | BIT(7) << 4;
101 d = BIT(22) << 4 | BITS(12,15);
102 //mm = SITOFP(32,RSPR(m));
103 //LETS(d,tmp);
104 mm = ZEXT64(IBITCAST32(FR32(2 * m)));
105 nn = ZEXT64(IBITCAST32(FR32(2 * m + 1)));
106 tmp = OR(SHL(nn,CONST64(32)),mm);
107 mm = FPBITCAST64(tmp);
108 tmp = ZEXT64(IBITCAST32(FR32(2 * n)));
109 nn = ZEXT64(IBITCAST32(FR32(2 * n + 1)));
110 nn = OR(SHL(nn,CONST64(32)),tmp);
111 nn = FPBITCAST64(nn);
112 tmp = FPMUL(nn,mm);
113 if(!add)
114 tmp = FPNEG64(tmp);
115 mm = ZEXT64(IBITCAST32(FR32(2 * d)));
116 nn = ZEXT64(IBITCAST32(FR32(2 * d + 1)));
117 mm = OR(SHL(nn,CONST64(32)),mm);
118 mm = FPBITCAST64(mm);
119 tmp = FPADD(mm,tmp);
120 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
121 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
122 LETFPS(2*d ,FPBITCAST32(nn));
123 LETFPS(d*2 + 1 , FPBITCAST32(mm));
124 }
125 return No_exp;
126}
127#endif
128
129/* ----------------------------------------------------------------------- */ 62/* ----------------------------------------------------------------------- */
130/* VNMLS */ 63/* VNMLS */
131/* cond 1110 0D00 Vn-- Vd-- 101X N1M0 Vm-- */ 64/* cond 1110 0D00 Vn-- Vd-- 101X N1M0 Vm-- */
@@ -176,74 +109,6 @@ VMLS_INST:
176} 109}
177#endif 110#endif
178 111
179#ifdef VFP_DYNCOM_TABLE
180DYNCOM_FILL_ACTION(vmls),
181#endif
182#ifdef VFP_DYNCOM_TAG
183int DYNCOM_TAG(vmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
184{
185 int instr_size = INSTR_SIZE;
186 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
187 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
188 return instr_size;
189}
190#endif
191#ifdef VFP_DYNCOM_TRANS
192int DYNCOM_TRANS(vmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
193 LOG_TRACE(Core_ARM11, "\t\tin %s VMLS instruction is executed out of here.\n", __FUNCTION__);
194 //arch_arm_undef(cpu, bb, instr);
195 int m;
196 int n;
197 int d ;
198 int add = (BIT(6) == 0);
199 int s = BIT(8) == 0;
200 Value *mm;
201 Value *nn;
202 Value *tmp;
203 if(s){
204 m = BIT(5) | BITS(0,3) << 1;
205 n = BIT(7) | BITS(16,19) << 1;
206 d = BIT(22) | BITS(12,15) << 1;
207 mm = FR32(m);
208 nn = FR32(n);
209 tmp = FPMUL(nn,mm);
210 if(!add)
211 tmp = FPNEG32(tmp);
212 mm = FR32(d);
213 tmp = FPADD(mm,tmp);
214 //LETS(d,tmp);
215 LETFPS(d,tmp);
216 }else {
217 m = BITS(0,3) | BIT(5) << 4;
218 n = BITS(16,19) | BIT(7) << 4;
219 d = BIT(22) << 4 | BITS(12,15);
220 //mm = SITOFP(32,RSPR(m));
221 //LETS(d,tmp);
222 mm = ZEXT64(IBITCAST32(FR32(2 * m)));
223 nn = ZEXT64(IBITCAST32(FR32(2 * m + 1)));
224 tmp = OR(SHL(nn,CONST64(32)),mm);
225 mm = FPBITCAST64(tmp);
226 tmp = ZEXT64(IBITCAST32(FR32(2 * n)));
227 nn = ZEXT64(IBITCAST32(FR32(2 * n + 1)));
228 nn = OR(SHL(nn,CONST64(32)),tmp);
229 nn = FPBITCAST64(nn);
230 tmp = FPMUL(nn,mm);
231 if(!add)
232 tmp = FPNEG64(tmp);
233 mm = ZEXT64(IBITCAST32(FR32(2 * d)));
234 nn = ZEXT64(IBITCAST32(FR32(2 * d + 1)));
235 mm = OR(SHL(nn,CONST64(32)),mm);
236 mm = FPBITCAST64(mm);
237 tmp = FPADD(mm,tmp);
238 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
239 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
240 LETFPS(2*d ,FPBITCAST32(nn));
241 LETFPS(d*2 + 1 , FPBITCAST32(mm));
242 }
243 return No_exp;
244}
245#endif
246
247/* ----------------------------------------------------------------------- */ 112/* ----------------------------------------------------------------------- */
248/* VNMLA */ 113/* VNMLA */
249/* cond 1110 0D01 Vn-- Vd-- 101X N1M0 Vm-- */ 114/* cond 1110 0D01 Vn-- Vd-- 101X N1M0 Vm-- */
@@ -294,75 +159,6 @@ VNMLA_INST:
294} 159}
295#endif 160#endif
296 161
297#ifdef VFP_DYNCOM_TABLE
298DYNCOM_FILL_ACTION(vnmla),
299DYNCOM_FILL_ACTION(vnmla),
300#endif
301#ifdef VFP_DYNCOM_TAG
302int DYNCOM_TAG(vnmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
303{
304 int instr_size = INSTR_SIZE;
305 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
306 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
307 return instr_size;
308}
309#endif
310#ifdef VFP_DYNCOM_TRANS
311int DYNCOM_TRANS(vnmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
312 LOG_TRACE(Core_ARM11, "\t\tin %s VNMLA instruction is executed out of here.\n", __FUNCTION__);
313 //arch_arm_undef(cpu, bb, instr);
314 int m;
315 int n;
316 int d ;
317 int add = (BIT(6) == 0);
318 int s = BIT(8) == 0;
319 Value *mm;
320 Value *nn;
321 Value *tmp;
322 if(s){
323 m = BIT(5) | BITS(0,3) << 1;
324 n = BIT(7) | BITS(16,19) << 1;
325 d = BIT(22) | BITS(12,15) << 1;
326 mm = FR32(m);
327 nn = FR32(n);
328 tmp = FPMUL(nn,mm);
329 if(!add)
330 tmp = FPNEG32(tmp);
331 mm = FR32(d);
332 tmp = FPADD(FPNEG32(mm),tmp);
333 //LETS(d,tmp);
334 LETFPS(d,tmp);
335 }else {
336 m = BITS(0,3) | BIT(5) << 4;
337 n = BITS(16,19) | BIT(7) << 4;
338 d = BIT(22) << 4 | BITS(12,15);
339 //mm = SITOFP(32,RSPR(m));
340 //LETS(d,tmp);
341 mm = ZEXT64(IBITCAST32(FR32(2 * m)));
342 nn = ZEXT64(IBITCAST32(FR32(2 * m + 1)));
343 tmp = OR(SHL(nn,CONST64(32)),mm);
344 mm = FPBITCAST64(tmp);
345 tmp = ZEXT64(IBITCAST32(FR32(2 * n)));
346 nn = ZEXT64(IBITCAST32(FR32(2 * n + 1)));
347 nn = OR(SHL(nn,CONST64(32)),tmp);
348 nn = FPBITCAST64(nn);
349 tmp = FPMUL(nn,mm);
350 if(!add)
351 tmp = FPNEG64(tmp);
352 mm = ZEXT64(IBITCAST32(FR32(2 * d)));
353 nn = ZEXT64(IBITCAST32(FR32(2 * d + 1)));
354 mm = OR(SHL(nn,CONST64(32)),mm);
355 mm = FPBITCAST64(mm);
356 tmp = FPADD(FPNEG64(mm),tmp);
357 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
358 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
359 LETFPS(2*d ,FPBITCAST32(nn));
360 LETFPS(d*2 + 1 , FPBITCAST32(mm));
361 }
362 return No_exp;
363}
364#endif
365
366/* ----------------------------------------------------------------------- */ 162/* ----------------------------------------------------------------------- */
367/* VNMLS */ 163/* VNMLS */
368/* cond 1110 0D01 Vn-- Vd-- 101X N0M0 Vm-- */ 164/* cond 1110 0D01 Vn-- Vd-- 101X N0M0 Vm-- */
@@ -414,75 +210,6 @@ VNMLS_INST:
414} 210}
415#endif 211#endif
416 212
417#ifdef VFP_DYNCOM_TABLE
418DYNCOM_FILL_ACTION(vnmls),
419#endif
420#ifdef VFP_DYNCOM_TAG
421int DYNCOM_TAG(vnmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
422{
423 int instr_size = INSTR_SIZE;
424 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
425 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
426 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
427 return instr_size;
428}
429#endif
430#ifdef VFP_DYNCOM_TRANS
431int DYNCOM_TRANS(vnmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
432 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
433 //arch_arm_undef(cpu, bb, instr);
434 int m;
435 int n;
436 int d ;
437 int add = (BIT(6) == 0);
438 int s = BIT(8) == 0;
439 Value *mm;
440 Value *nn;
441 Value *tmp;
442 if(s){
443 m = BIT(5) | BITS(0,3) << 1;
444 n = BIT(7) | BITS(16,19) << 1;
445 d = BIT(22) | BITS(12,15) << 1;
446 mm = FR32(m);
447 nn = FR32(n);
448 tmp = FPMUL(nn,mm);
449 if(!add)
450 tmp = FPNEG32(tmp);
451 mm = FR32(d);
452 tmp = FPADD(FPNEG32(mm),tmp);
453 //LETS(d,tmp);
454 LETFPS(d,tmp);
455 }else {
456 m = BITS(0,3) | BIT(5) << 4;
457 n = BITS(16,19) | BIT(7) << 4;
458 d = BIT(22) << 4 | BITS(12,15);
459 //mm = SITOFP(32,RSPR(m));
460 //LETS(d,tmp);
461 mm = ZEXT64(IBITCAST32(FR32(2 * m)));
462 nn = ZEXT64(IBITCAST32(FR32(2 * m + 1)));
463 tmp = OR(SHL(nn,CONST64(32)),mm);
464 mm = FPBITCAST64(tmp);
465 tmp = ZEXT64(IBITCAST32(FR32(2 * n)));
466 nn = ZEXT64(IBITCAST32(FR32(2 * n + 1)));
467 nn = OR(SHL(nn,CONST64(32)),tmp);
468 nn = FPBITCAST64(nn);
469 tmp = FPMUL(nn,mm);
470 if(!add)
471 tmp = FPNEG64(tmp);
472 mm = ZEXT64(IBITCAST32(FR32(2 * d)));
473 nn = ZEXT64(IBITCAST32(FR32(2 * d + 1)));
474 mm = OR(SHL(nn,CONST64(32)),mm);
475 mm = FPBITCAST64(mm);
476 tmp = FPADD(FPNEG64(mm),tmp);
477 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
478 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
479 LETFPS(2*d ,FPBITCAST32(nn));
480 LETFPS(d*2 + 1 , FPBITCAST32(mm));
481 }
482 return No_exp;
483}
484#endif
485
486/* ----------------------------------------------------------------------- */ 213/* ----------------------------------------------------------------------- */
487/* VNMUL */ 214/* VNMUL */
488/* cond 1110 0D10 Vn-- Vd-- 101X N0M0 Vm-- */ 215/* cond 1110 0D10 Vn-- Vd-- 101X N0M0 Vm-- */
@@ -533,65 +260,6 @@ VNMUL_INST:
533} 260}
534#endif 261#endif
535 262
536#ifdef VFP_DYNCOM_TABLE
537DYNCOM_FILL_ACTION(vnmul),
538#endif
539#ifdef VFP_DYNCOM_TAG
540int DYNCOM_TAG(vnmul)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
541{
542 int instr_size = INSTR_SIZE;
543 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
544 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
545 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
546 return instr_size;
547}
548#endif
549#ifdef VFP_DYNCOM_TRANS
550int DYNCOM_TRANS(vnmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
551 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
552 //arch_arm_undef(cpu, bb, instr);
553 int m;
554 int n;
555 int d ;
556 int add = (BIT(6) == 0);
557 int s = BIT(8) == 0;
558 Value *mm;
559 Value *nn;
560 Value *tmp;
561 if(s){
562 m = BIT(5) | BITS(0,3) << 1;
563 n = BIT(7) | BITS(16,19) << 1;
564 d = BIT(22) | BITS(12,15) << 1;
565 mm = FR32(m);
566 nn = FR32(n);
567 tmp = FPMUL(nn,mm);
568 //LETS(d,tmp);
569 LETFPS(d,FPNEG32(tmp));
570 }else {
571 m = BITS(0,3) | BIT(5) << 4;
572 n = BITS(16,19) | BIT(7) << 4;
573 d = BIT(22) << 4 | BITS(12,15);
574 //mm = SITOFP(32,RSPR(m));
575 //LETS(d,tmp);
576 mm = ZEXT64(IBITCAST32(FR32(2 * m)));
577 nn = ZEXT64(IBITCAST32(FR32(2 * m + 1)));
578 tmp = OR(SHL(nn,CONST64(32)),mm);
579 mm = FPBITCAST64(tmp);
580 tmp = ZEXT64(IBITCAST32(FR32(2 * n)));
581 nn = ZEXT64(IBITCAST32(FR32(2 * n + 1)));
582 nn = OR(SHL(nn,CONST64(32)),tmp);
583 nn = FPBITCAST64(nn);
584 tmp = FPMUL(nn,mm);
585 tmp = FPNEG64(tmp);
586 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
587 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
588 LETFPS(2*d ,FPBITCAST32(nn));
589 LETFPS(d*2 + 1 , FPBITCAST32(mm));
590 }
591 return No_exp;
592}
593#endif
594
595/* ----------------------------------------------------------------------- */ 263/* ----------------------------------------------------------------------- */
596/* VMUL */ 264/* VMUL */
597/* cond 1110 0D10 Vn-- Vd-- 101X N0M0 Vm-- */ 265/* cond 1110 0D10 Vn-- Vd-- 101X N0M0 Vm-- */
@@ -642,77 +310,6 @@ VMUL_INST:
642} 310}
643#endif 311#endif
644 312
645#ifdef VFP_DYNCOM_TABLE
646DYNCOM_FILL_ACTION(vmul),
647#endif
648#ifdef VFP_DYNCOM_TAG
649int DYNCOM_TAG(vmul)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
650{
651 int instr_size = INSTR_SIZE;
652 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
653 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
654 return instr_size;
655}
656#endif
657#ifdef VFP_DYNCOM_TRANS
658int DYNCOM_TRANS(vmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
659 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
660 //arch_arm_undef(cpu, bb, instr);
661 int m;
662 int n;
663 int d ;
664 int s = BIT(8) == 0;
665 Value *mm;
666 Value *nn;
667 Value *tmp;
668 if(s){
669 m = BIT(5) | BITS(0,3) << 1;
670 n = BIT(7) | BITS(16,19) << 1;
671 d = BIT(22) | BITS(12,15) << 1;
672 //mm = SITOFP(32,FR(m));
673 //nn = SITOFP(32,FRn));
674 mm = FR32(m);
675 nn = FR32(n);
676 tmp = FPMUL(nn,mm);
677 //LETS(d,tmp);
678 LETFPS(d,tmp);
679 }else {
680 m = BITS(0,3) | BIT(5) << 4;
681 n = BITS(16,19) | BIT(7) << 4;
682 d = BIT(22) << 4 | BITS(12,15);
683 //mm = SITOFP(32,RSPR(m));
684 //LETS(d,tmp);
685 Value *lo = FR32(2 * m);
686 Value *hi = FR32(2 * m + 1);
687 hi = IBITCAST32(hi);
688 lo = IBITCAST32(lo);
689 Value *hi64 = ZEXT64(hi);
690 Value* lo64 = ZEXT64(lo);
691 Value* v64 = OR(SHL(hi64,CONST64(32)),lo64);
692 Value* m0 = FPBITCAST64(v64);
693 lo = FR32(2 * n);
694 hi = FR32(2 * n + 1);
695 hi = IBITCAST32(hi);
696 lo = IBITCAST32(lo);
697 hi64 = ZEXT64(hi);
698 lo64 = ZEXT64(lo);
699 v64 = OR(SHL(hi64,CONST64(32)),lo64);
700 Value *n0 = FPBITCAST64(v64);
701 tmp = FPMUL(n0,m0);
702 Value *val64 = IBITCAST64(tmp);
703 hi = LSHR(val64,CONST64(32));
704 lo = AND(val64,CONST64(0xffffffff));
705 hi = TRUNC32(hi);
706 lo = TRUNC32(lo);
707 hi = FPBITCAST32(hi);
708 lo = FPBITCAST32(lo);
709 LETFPS(2*d ,lo);
710 LETFPS(d*2 + 1 , hi);
711 }
712 return No_exp;
713}
714#endif
715
716/* ----------------------------------------------------------------------- */ 313/* ----------------------------------------------------------------------- */
717/* VADD */ 314/* VADD */
718/* cond 1110 0D11 Vn-- Vd-- 101X N0M0 Vm-- */ 315/* cond 1110 0D11 Vn-- Vd-- 101X N0M0 Vm-- */
@@ -763,73 +360,6 @@ VADD_INST:
763} 360}
764#endif 361#endif
765 362
766#ifdef VFP_DYNCOM_TABLE
767DYNCOM_FILL_ACTION(vadd),
768#endif
769#ifdef VFP_DYNCOM_TAG
770int DYNCOM_TAG(vadd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
771{
772 int instr_size = INSTR_SIZE;
773 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
774 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
775 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
776 return instr_size;
777}
778#endif
779#ifdef VFP_DYNCOM_TRANS
780int DYNCOM_TRANS(vadd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
781 LOG_TRACE(Core_ARM11, "\t\tin %s instruction will implement out of JIT.\n", __FUNCTION__);
782 //arch_arm_undef(cpu, bb, instr);
783 int m;
784 int n;
785 int d ;
786 int s = BIT(8) == 0;
787 Value *mm;
788 Value *nn;
789 Value *tmp;
790 if(s){
791 m = BIT(5) | BITS(0,3) << 1;
792 n = BIT(7) | BITS(16,19) << 1;
793 d = BIT(22) | BITS(12,15) << 1;
794 mm = FR32(m);
795 nn = FR32(n);
796 tmp = FPADD(nn,mm);
797 LETFPS(d,tmp);
798 }else {
799 m = BITS(0,3) | BIT(5) << 4;
800 n = BITS(16,19) | BIT(7) << 4;
801 d = BIT(22) << 4 | BITS(12,15);
802 Value *lo = FR32(2 * m);
803 Value *hi = FR32(2 * m + 1);
804 hi = IBITCAST32(hi);
805 lo = IBITCAST32(lo);
806 Value *hi64 = ZEXT64(hi);
807 Value* lo64 = ZEXT64(lo);
808 Value* v64 = OR(SHL(hi64,CONST64(32)),lo64);
809 Value* m0 = FPBITCAST64(v64);
810 lo = FR32(2 * n);
811 hi = FR32(2 * n + 1);
812 hi = IBITCAST32(hi);
813 lo = IBITCAST32(lo);
814 hi64 = ZEXT64(hi);
815 lo64 = ZEXT64(lo);
816 v64 = OR(SHL(hi64,CONST64(32)),lo64);
817 Value *n0 = FPBITCAST64(v64);
818 tmp = FPADD(n0,m0);
819 Value *val64 = IBITCAST64(tmp);
820 hi = LSHR(val64,CONST64(32));
821 lo = AND(val64,CONST64(0xffffffff));
822 hi = TRUNC32(hi);
823 lo = TRUNC32(lo);
824 hi = FPBITCAST32(hi);
825 lo = FPBITCAST32(lo);
826 LETFPS(2*d ,lo);
827 LETFPS(d*2 + 1 , hi);
828 }
829 return No_exp;
830}
831#endif
832
833/* ----------------------------------------------------------------------- */ 363/* ----------------------------------------------------------------------- */
834/* VSUB */ 364/* VSUB */
835/* cond 1110 0D11 Vn-- Vd-- 101X N1M0 Vm-- */ 365/* cond 1110 0D11 Vn-- Vd-- 101X N1M0 Vm-- */
@@ -879,71 +409,6 @@ VSUB_INST:
879 GOTO_NEXT_INST; 409 GOTO_NEXT_INST;
880} 410}
881#endif 411#endif
882#ifdef VFP_DYNCOM_TABLE
883DYNCOM_FILL_ACTION(vsub),
884#endif
885#ifdef VFP_DYNCOM_TAG
886int DYNCOM_TAG(vsub)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
887{
888 int instr_size = INSTR_SIZE;
889 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
890 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
891 return instr_size;
892}
893#endif
894#ifdef VFP_DYNCOM_TRANS
895int DYNCOM_TRANS(vsub)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
896 LOG_TRACE(Core_ARM11, "\t\tin %s instr=0x%x, instruction is executed out of JIT.\n", __FUNCTION__, instr);
897 //arch_arm_undef(cpu, bb, instr);
898 int m;
899 int n;
900 int d ;
901 int s = BIT(8) == 0;
902 Value *mm;
903 Value *nn;
904 Value *tmp;
905 if(s){
906 m = BIT(5) | BITS(0,3) << 1;
907 n = BIT(7) | BITS(16,19) << 1;
908 d = BIT(22) | BITS(12,15) << 1;
909 mm = FR32(m);
910 nn = FR32(n);
911 tmp = FPSUB(nn,mm);
912 LETFPS(d,tmp);
913 }else {
914 m = BITS(0,3) | BIT(5) << 4;
915 n = BITS(16,19) | BIT(7) << 4;
916 d = BIT(22) << 4 | BITS(12,15);
917 Value *lo = FR32(2 * m);
918 Value *hi = FR32(2 * m + 1);
919 hi = IBITCAST32(hi);
920 lo = IBITCAST32(lo);
921 Value *hi64 = ZEXT64(hi);
922 Value* lo64 = ZEXT64(lo);
923 Value* v64 = OR(SHL(hi64,CONST64(32)),lo64);
924 Value* m0 = FPBITCAST64(v64);
925 lo = FR32(2 * n);
926 hi = FR32(2 * n + 1);
927 hi = IBITCAST32(hi);
928 lo = IBITCAST32(lo);
929 hi64 = ZEXT64(hi);
930 lo64 = ZEXT64(lo);
931 v64 = OR(SHL(hi64,CONST64(32)),lo64);
932 Value *n0 = FPBITCAST64(v64);
933 tmp = FPSUB(n0,m0);
934 Value *val64 = IBITCAST64(tmp);
935 hi = LSHR(val64,CONST64(32));
936 lo = AND(val64,CONST64(0xffffffff));
937 hi = TRUNC32(hi);
938 lo = TRUNC32(lo);
939 hi = FPBITCAST32(hi);
940 lo = FPBITCAST32(lo);
941 LETFPS(2*d ,lo);
942 LETFPS(d*2 + 1 , hi);
943 }
944 return No_exp;
945}
946#endif
947 412
948/* ----------------------------------------------------------------------- */ 413/* ----------------------------------------------------------------------- */
949/* VDIV */ 414/* VDIV */
@@ -995,73 +460,6 @@ VDIV_INST:
995} 460}
996#endif 461#endif
997 462
998#ifdef VFP_DYNCOM_TABLE
999DYNCOM_FILL_ACTION(vdiv),
1000#endif
1001#ifdef VFP_DYNCOM_TAG
1002int DYNCOM_TAG(vdiv)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1003{
1004 int instr_size = INSTR_SIZE;
1005 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1006 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1007 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1008 return instr_size;
1009}
1010#endif
1011#ifdef VFP_DYNCOM_TRANS
1012int DYNCOM_TRANS(vdiv)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1013 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1014 //arch_arm_undef(cpu, bb, instr);
1015 int m;
1016 int n;
1017 int d ;
1018 int s = BIT(8) == 0;
1019 Value *mm;
1020 Value *nn;
1021 Value *tmp;
1022 if(s){
1023 m = BIT(5) | BITS(0,3) << 1;
1024 n = BIT(7) | BITS(16,19) << 1;
1025 d = BIT(22) | BITS(12,15) << 1;
1026 mm = FR32(m);
1027 nn = FR32(n);
1028 tmp = FPDIV(nn,mm);
1029 LETFPS(d,tmp);
1030 }else {
1031 m = BITS(0,3) | BIT(5) << 4;
1032 n = BITS(16,19) | BIT(7) << 4;
1033 d = BIT(22) << 4 | BITS(12,15);
1034 Value *lo = FR32(2 * m);
1035 Value *hi = FR32(2 * m + 1);
1036 hi = IBITCAST32(hi);
1037 lo = IBITCAST32(lo);
1038 Value *hi64 = ZEXT64(hi);
1039 Value* lo64 = ZEXT64(lo);
1040 Value* v64 = OR(SHL(hi64,CONST64(32)),lo64);
1041 Value* m0 = FPBITCAST64(v64);
1042 lo = FR32(2 * n);
1043 hi = FR32(2 * n + 1);
1044 hi = IBITCAST32(hi);
1045 lo = IBITCAST32(lo);
1046 hi64 = ZEXT64(hi);
1047 lo64 = ZEXT64(lo);
1048 v64 = OR(SHL(hi64,CONST64(32)),lo64);
1049 Value *n0 = FPBITCAST64(v64);
1050 tmp = FPDIV(n0,m0);
1051 Value *val64 = IBITCAST64(tmp);
1052 hi = LSHR(val64,CONST64(32));
1053 lo = AND(val64,CONST64(0xffffffff));
1054 hi = TRUNC32(hi);
1055 lo = TRUNC32(lo);
1056 hi = FPBITCAST32(hi);
1057 lo = FPBITCAST32(lo);
1058 LETFPS(2*d ,lo);
1059 LETFPS(d*2 + 1 , hi);
1060 }
1061 return No_exp;
1062}
1063#endif
1064
1065/* ----------------------------------------------------------------------- */ 463/* ----------------------------------------------------------------------- */
1066/* VMOVI move immediate */ 464/* VMOVI move immediate */
1067/* cond 1110 1D11 im4H Vd-- 101X 0000 im4L */ 465/* cond 1110 1D11 im4H Vd-- 101X 0000 im4L */
@@ -1111,46 +509,6 @@ VMOVI_INST:
1111} 509}
1112#endif 510#endif
1113 511
1114#ifdef VFP_DYNCOM_TABLE
1115DYNCOM_FILL_ACTION(vmovi),
1116#endif
1117#ifdef VFP_DYNCOM_TAG
1118int DYNCOM_TAG(vmovi)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1119{
1120 int instr_size = INSTR_SIZE;
1121 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1122 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1123 return instr_size;
1124}
1125#endif
1126#ifdef VFP_DYNCOM_TRANS
1127int DYNCOM_TRANS(vmovi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1128 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1129 //arch_arm_undef(cpu, bb, instr);
1130 int single = (BIT(8) == 0);
1131 int d;
1132 int imm32;
1133 Value *v;
1134 Value *tmp;
1135 v = CONST32(BITS(0,3) | BITS(16,19) << 4);
1136 //v = CONST64(0x3ff0000000000000);
1137 if(single){
1138 d = BIT(22) | BITS(12,15) << 1;
1139 }else {
1140 d = BITS(12,15) | BIT(22) << 4;
1141 }
1142 if(single){
1143 LETFPS(d,FPBITCAST32(v));
1144 }else {
1145 //v = UITOFP(64,v);
1146 //tmp = IBITCAST64(v);
1147 LETFPS(d*2 ,FPBITCAST32(TRUNC32(AND(v,CONST64(0xffffffff)))));
1148 LETFPS(d * 2 + 1,FPBITCAST32(TRUNC32(LSHR(v,CONST64(32)))));
1149 }
1150 return No_exp;
1151}
1152#endif
1153
1154/* ----------------------------------------------------------------------- */ 512/* ----------------------------------------------------------------------- */
1155/* VMOVR move register */ 513/* VMOVR move register */
1156/* cond 1110 1D11 0000 Vd-- 101X 01M0 Vm-- */ 514/* cond 1110 1D11 0000 Vd-- 101X 01M0 Vm-- */
@@ -1196,40 +554,6 @@ VMOVR_INST:
1196} 554}
1197#endif 555#endif
1198 556
1199#ifdef VFP_DYNCOM_TABLE
1200DYNCOM_FILL_ACTION(vmovr),
1201#endif
1202#ifdef VFP_DYNCOM_TAG
1203int DYNCOM_TAG(vmovr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1204{
1205 int instr_size = INSTR_SIZE;
1206 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1207 if(instr >> 28 != 0xe)
1208 *tag |= TAG_CONDITIONAL;
1209
1210 return instr_size;
1211}
1212#endif
1213#ifdef VFP_DYNCOM_TRANS
1214int DYNCOM_TRANS(vmovr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1215 int single = BIT(8) == 0;
1216 int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15));
1217 int m = (single ? BITS(0, 3)<<1 | BIT(5) : BITS(0, 3) | BIT(5)<<4);
1218
1219 if (single)
1220 {
1221 LETFPS(d, FR32(m));
1222 }
1223 else
1224 {
1225 /* Check endian please */
1226 LETFPS((d*2 + 1), FR32(m*2 + 1));
1227 LETFPS((d * 2), FR32(m * 2));
1228 }
1229 return No_exp;
1230}
1231#endif
1232
1233/* ----------------------------------------------------------------------- */ 557/* ----------------------------------------------------------------------- */
1234/* VABS */ 558/* VABS */
1235/* cond 1110 1D11 0000 Vd-- 101X 11M0 Vm-- */ 559/* cond 1110 1D11 0000 Vd-- 101X 11M0 Vm-- */
@@ -1280,57 +604,6 @@ VABS_INST:
1280} 604}
1281#endif 605#endif
1282 606
1283#ifdef VFP_DYNCOM_TABLE
1284DYNCOM_FILL_ACTION(vabs),
1285#endif
1286#ifdef VFP_DYNCOM_TAG
1287int DYNCOM_TAG(vabs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1288{
1289 int instr_size = INSTR_SIZE;
1290 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1291 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1292 return instr_size;
1293}
1294#endif
1295#ifdef VFP_DYNCOM_TRANS
1296int DYNCOM_TRANS(vabs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1297 //arch_arm_undef(cpu, bb, instr);
1298 int single = BIT(8) == 0;
1299 int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15));
1300 int m = (single ? BITS(0, 3)<<1 | BIT(5) : BITS(0, 3) | BIT(5)<<4);
1301 Value* m0;
1302 if (single)
1303 {
1304 m0 = FR32(m);
1305 m0 = SELECT(FPCMP_OLT(m0,FPCONST32(0.0)),FPNEG32(m0),m0);
1306 LETFPS(d,m0);
1307 }
1308 else
1309 {
1310 /* Check endian please */
1311 Value *lo = FR32(2 * m);
1312 Value *hi = FR32(2 * m + 1);
1313 hi = IBITCAST32(hi);
1314 lo = IBITCAST32(lo);
1315 Value *hi64 = ZEXT64(hi);
1316 Value* lo64 = ZEXT64(lo);
1317 Value* v64 = OR(SHL(hi64,CONST64(32)),lo64);
1318 m0 = FPBITCAST64(v64);
1319 m0 = SELECT(FPCMP_OLT(m0,FPCONST64(0.0)),FPNEG64(m0),m0);
1320 Value *val64 = IBITCAST64(m0);
1321 hi = LSHR(val64,CONST64(32));
1322 lo = AND(val64,CONST64(0xffffffff));
1323 hi = TRUNC32(hi);
1324 lo = TRUNC32(lo);
1325 hi = FPBITCAST32(hi);
1326 lo = FPBITCAST32(lo);
1327 LETFPS(2*d ,lo);
1328 LETFPS(d*2 + 1 , hi);
1329 }
1330 return No_exp;
1331}
1332#endif
1333
1334/* ----------------------------------------------------------------------- */ 607/* ----------------------------------------------------------------------- */
1335/* VNEG */ 608/* VNEG */
1336/* cond 1110 1D11 0001 Vd-- 101X 11M0 Vm-- */ 609/* cond 1110 1D11 0001 Vd-- 101X 11M0 Vm-- */
@@ -1382,59 +655,6 @@ VNEG_INST:
1382} 655}
1383#endif 656#endif
1384 657
1385#ifdef VFP_DYNCOM_TABLE
1386DYNCOM_FILL_ACTION(vneg),
1387#endif
1388#ifdef VFP_DYNCOM_TAG
1389int DYNCOM_TAG(vneg)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1390{
1391 int instr_size = INSTR_SIZE;
1392 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1393 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1394 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1395 return instr_size;
1396}
1397#endif
1398#ifdef VFP_DYNCOM_TRANS
1399int DYNCOM_TRANS(vneg)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1400 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1401 //arch_arm_undef(cpu, bb, instr);
1402 int single = BIT(8) == 0;
1403 int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15));
1404 int m = (single ? BITS(0, 3)<<1 | BIT(5) : BITS(0, 3) | BIT(5)<<4);
1405 Value* m0;
1406 if (single)
1407 {
1408 m0 = FR32(m);
1409 m0 = FPNEG32(m0);
1410 LETFPS(d,m0);
1411 }
1412 else
1413 {
1414 /* Check endian please */
1415 Value *lo = FR32(2 * m);
1416 Value *hi = FR32(2 * m + 1);
1417 hi = IBITCAST32(hi);
1418 lo = IBITCAST32(lo);
1419 Value *hi64 = ZEXT64(hi);
1420 Value* lo64 = ZEXT64(lo);
1421 Value* v64 = OR(SHL(hi64,CONST64(32)),lo64);
1422 m0 = FPBITCAST64(v64);
1423 m0 = FPNEG64(m0);
1424 Value *val64 = IBITCAST64(m0);
1425 hi = LSHR(val64,CONST64(32));
1426 lo = AND(val64,CONST64(0xffffffff));
1427 hi = TRUNC32(hi);
1428 lo = TRUNC32(lo);
1429 hi = FPBITCAST32(hi);
1430 lo = FPBITCAST32(lo);
1431 LETFPS(2*d ,lo);
1432 LETFPS(d*2 + 1 , hi);
1433 }
1434 return No_exp;
1435}
1436#endif
1437
1438/* ----------------------------------------------------------------------- */ 658/* ----------------------------------------------------------------------- */
1439/* VSQRT */ 659/* VSQRT */
1440/* cond 1110 1D11 0001 Vd-- 101X 11M0 Vm-- */ 660/* cond 1110 1D11 0001 Vd-- 101X 11M0 Vm-- */
@@ -1485,47 +705,6 @@ VSQRT_INST:
1485} 705}
1486#endif 706#endif
1487 707
1488#ifdef VFP_DYNCOM_TABLE
1489DYNCOM_FILL_ACTION(vsqrt),
1490#endif
1491#ifdef VFP_DYNCOM_TAG
1492int DYNCOM_TAG(vsqrt)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1493{
1494 int instr_size = INSTR_SIZE;
1495 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1496 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1497 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1498 return instr_size;
1499}
1500#endif
1501#ifdef VFP_DYNCOM_TRANS
1502int DYNCOM_TRANS(vsqrt)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1503 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1504 //arch_arm_undef(cpu, bb, instr);
1505 int dp_op = (BIT(8) == 1);
1506 int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1;
1507 int m = dp_op ? BITS(0,3) | BIT(5) << 4 : BIT(5) | BITS(0,3) << 1;
1508 Value* v;
1509 Value* tmp;
1510 if(dp_op){
1511 v = SHL(ZEXT64(IBITCAST32(FR32(2 * m + 1))),CONST64(32));
1512 tmp = ZEXT64(IBITCAST32(FR32(2 * m)));
1513 v = OR(v,tmp);
1514 v = FPSQRT(FPBITCAST64(v));
1515 tmp = TRUNC32(LSHR(IBITCAST64(v),CONST64(32)));
1516 v = TRUNC32(AND(IBITCAST64(v),CONST64( 0xffffffff)));
1517 LETFPS(2 * d , FPBITCAST32(v));
1518 LETFPS(2 * d + 1, FPBITCAST32(tmp));
1519 }else {
1520 v = FR32(m);
1521 v = FPSQRT(FPEXT(64,v));
1522 v = FPTRUNC(32,v);
1523 LETFPS(d,v);
1524 }
1525 return No_exp;
1526}
1527#endif
1528
1529/* ----------------------------------------------------------------------- */ 708/* ----------------------------------------------------------------------- */
1530/* VCMP VCMPE */ 709/* VCMP VCMPE */
1531/* cond 1110 1D11 0100 Vd-- 101X E1M0 Vm-- Encoding 1 */ 710/* cond 1110 1D11 0100 Vd-- 101X E1M0 Vm-- Encoding 1 */
@@ -1576,74 +755,6 @@ VCMP_INST:
1576} 755}
1577#endif 756#endif
1578 757
1579#ifdef VFP_DYNCOM_TABLE
1580DYNCOM_FILL_ACTION(vcmp),
1581#endif
1582#ifdef VFP_DYNCOM_TAG
1583int DYNCOM_TAG(vcmp)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1584{
1585 int instr_size = INSTR_SIZE;
1586 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1587 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1588 return instr_size;
1589}
1590#endif
1591#ifdef VFP_DYNCOM_TRANS
1592int DYNCOM_TRANS(vcmp)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1593 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is executed out of JIT.\n", __FUNCTION__);
1594 //arch_arm_undef(cpu, bb, instr);
1595 int dp_op = (BIT(8) == 1);
1596 int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1;
1597 int m = dp_op ? BITS(0,3) | BIT(5) << 4 : BIT(5) | BITS(0,3) << 1;
1598 Value* v;
1599 Value* tmp;
1600 Value* n;
1601 Value* z;
1602 Value* c;
1603 Value* vt;
1604 Value* v1;
1605 Value* nzcv;
1606 if(dp_op){
1607 v = SHL(ZEXT64(IBITCAST32(FR32(2 * m + 1))),CONST64(32));
1608 tmp = ZEXT64(IBITCAST32(FR32(2 * m)));
1609 v1 = OR(v,tmp);
1610 v = SHL(ZEXT64(IBITCAST32(FR32(2 * d + 1))),CONST64(32));
1611 tmp = ZEXT64(IBITCAST32(FR32(2 * d)));
1612 v = OR(v,tmp);
1613 z = FPCMP_OEQ(FPBITCAST64(v),FPBITCAST64(v1));
1614 n = FPCMP_OLT(FPBITCAST64(v),FPBITCAST64(v1));
1615 c = FPCMP_OGE(FPBITCAST64(v),FPBITCAST64(v1));
1616 tmp = FPCMP_UNO(FPBITCAST64(v),FPBITCAST64(v1));
1617 v1 = tmp;
1618 c = OR(c,tmp);
1619 n = SHL(ZEXT32(n),CONST32(31));
1620 z = SHL(ZEXT32(z),CONST32(30));
1621 c = SHL(ZEXT32(c),CONST32(29));
1622 v1 = SHL(ZEXT32(v1),CONST(28));
1623 nzcv = OR(OR(OR(n,z),c),v1);
1624 v = R(VFP_FPSCR);
1625 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
1626 LET(VFP_FPSCR,tmp);
1627 }else {
1628 z = FPCMP_OEQ(FR32(d),FR32(m));
1629 n = FPCMP_OLT(FR32(d),FR32(m));
1630 c = FPCMP_OGE(FR32(d),FR32(m));
1631 tmp = FPCMP_UNO(FR32(d),FR32(m));
1632 c = OR(c,tmp);
1633 v1 = tmp;
1634 n = SHL(ZEXT32(n),CONST32(31));
1635 z = SHL(ZEXT32(z),CONST32(30));
1636 c = SHL(ZEXT32(c),CONST32(29));
1637 v1 = SHL(ZEXT32(v1),CONST(28));
1638 nzcv = OR(OR(OR(n,z),c),v1);
1639 v = R(VFP_FPSCR);
1640 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
1641 LET(VFP_FPSCR,tmp);
1642 }
1643 return No_exp;
1644}
1645#endif
1646
1647/* ----------------------------------------------------------------------- */ 758/* ----------------------------------------------------------------------- */
1648/* VCMP VCMPE */ 759/* VCMP VCMPE */
1649/* cond 1110 1D11 0100 Vd-- 101X E1M0 Vm-- Encoding 2 */ 760/* cond 1110 1D11 0100 Vd-- 101X E1M0 Vm-- Encoding 2 */
@@ -1694,74 +805,6 @@ VCMP2_INST:
1694} 805}
1695#endif 806#endif
1696 807
1697#ifdef VFP_DYNCOM_TABLE
1698DYNCOM_FILL_ACTION(vcmp2),
1699#endif
1700#ifdef VFP_DYNCOM_TAG
1701int DYNCOM_TAG(vcmp2)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1702{
1703 int instr_size = INSTR_SIZE;
1704 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1705 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1706 return instr_size;
1707}
1708#endif
1709#ifdef VFP_DYNCOM_TRANS
1710int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1711 LOG_TRACE(Core_ARM11, "\t\tin %s instruction will executed out of JIT.\n", __FUNCTION__);
1712 //arch_arm_undef(cpu, bb, instr);
1713 int dp_op = (BIT(8) == 1);
1714 int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1;
1715 //int m = dp_op ? BITS(0,3) | BIT(5) << 4 : BIT(5) | BITS(0,3) << 1;
1716 Value* v;
1717 Value* tmp;
1718 Value* n;
1719 Value* z;
1720 Value* c;
1721 Value* vt;
1722 Value* v1;
1723 Value* nzcv;
1724 if(dp_op){
1725 v1 = CONST64(0);
1726 v = SHL(ZEXT64(IBITCAST32(FR32(2 * d + 1))),CONST64(32));
1727 tmp = ZEXT64(IBITCAST32(FR32(2 * d)));
1728 v = OR(v,tmp);
1729 z = FPCMP_OEQ(FPBITCAST64(v),FPBITCAST64(v1));
1730 n = FPCMP_OLT(FPBITCAST64(v),FPBITCAST64(v1));
1731 c = FPCMP_OGE(FPBITCAST64(v),FPBITCAST64(v1));
1732 tmp = FPCMP_UNO(FPBITCAST64(v),FPBITCAST64(v1));
1733 v1 = tmp;
1734 c = OR(c,tmp);
1735 n = SHL(ZEXT32(n),CONST32(31));
1736 z = SHL(ZEXT32(z),CONST32(30));
1737 c = SHL(ZEXT32(c),CONST32(29));
1738 v1 = SHL(ZEXT32(v1),CONST(28));
1739 nzcv = OR(OR(OR(n,z),c),v1);
1740 v = R(VFP_FPSCR);
1741 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
1742 LET(VFP_FPSCR,tmp);
1743 }else {
1744 v1 = CONST(0);
1745 v1 = FPBITCAST32(v1);
1746 z = FPCMP_OEQ(FR32(d),v1);
1747 n = FPCMP_OLT(FR32(d),v1);
1748 c = FPCMP_OGE(FR32(d),v1);
1749 tmp = FPCMP_UNO(FR32(d),v1);
1750 c = OR(c,tmp);
1751 v1 = tmp;
1752 n = SHL(ZEXT32(n),CONST32(31));
1753 z = SHL(ZEXT32(z),CONST32(30));
1754 c = SHL(ZEXT32(c),CONST32(29));
1755 v1 = SHL(ZEXT32(v1),CONST(28));
1756 nzcv = OR(OR(OR(n,z),c),v1);
1757 v = R(VFP_FPSCR);
1758 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
1759 LET(VFP_FPSCR,tmp);
1760 }
1761 return No_exp;
1762}
1763#endif
1764
1765/* ----------------------------------------------------------------------- */ 808/* ----------------------------------------------------------------------- */
1766/* VCVTBDS between double and single */ 809/* VCVTBDS between double and single */
1767/* cond 1110 1D11 0111 Vd-- 101X 11M0 Vm-- */ 810/* cond 1110 1D11 0111 Vd-- 101X 11M0 Vm-- */
@@ -1812,48 +855,6 @@ VCVTBDS_INST:
1812} 855}
1813#endif 856#endif
1814 857
1815#ifdef VFP_DYNCOM_TABLE
1816DYNCOM_FILL_ACTION(vcvtbds),
1817#endif
1818#ifdef VFP_DYNCOM_TAG
1819int DYNCOM_TAG(vcvtbds)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1820{
1821 int instr_size = INSTR_SIZE;
1822 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1823 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1824 return instr_size;
1825}
1826#endif
1827#ifdef VFP_DYNCOM_TRANS
1828int DYNCOM_TRANS(vcvtbds)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1829 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is executed out.\n", __FUNCTION__);
1830 //arch_arm_undef(cpu, bb, instr);
1831 int dp_op = (BIT(8) == 1);
1832 int d = dp_op ? BITS(12,15) << 1 | BIT(22) : BIT(22) << 4 | BITS(12,15);
1833 int m = dp_op ? BITS(0,3) | BIT(5) << 4 : BIT(5) | BITS(0,3) << 1;
1834 int d2s = dp_op;
1835 Value* v;
1836 Value* tmp;
1837 Value* v1;
1838 if(d2s){
1839 v = SHL(ZEXT64(IBITCAST32(FR32(2 * m + 1))),CONST64(32));
1840 tmp = ZEXT64(IBITCAST32(FR32(2 * m)));
1841 v1 = OR(v,tmp);
1842 tmp = FPTRUNC(32,FPBITCAST64(v1));
1843 LETFPS(d,tmp);
1844 }else {
1845 v = FR32(m);
1846 tmp = FPEXT(64,v);
1847 v = IBITCAST64(tmp);
1848 tmp = TRUNC32(AND(v,CONST64(0xffffffff)));
1849 v1 = TRUNC32(LSHR(v,CONST64(32)));
1850 LETFPS(2 * d, FPBITCAST32(tmp) );
1851 LETFPS(2 * d + 1, FPBITCAST32(v1));
1852 }
1853 return No_exp;
1854}
1855#endif
1856
1857/* ----------------------------------------------------------------------- */ 858/* ----------------------------------------------------------------------- */
1858/* VCVTBFF between floating point and fixed point */ 859/* VCVTBFF between floating point and fixed point */
1859/* cond 1110 1D11 1op2 Vd-- 101X X1M0 Vm-- */ 860/* cond 1110 1D11 1op2 Vd-- 101X X1M0 Vm-- */
@@ -1906,26 +907,6 @@ VCVTBFF_INST:
1906} 907}
1907#endif 908#endif
1908 909
1909#ifdef VFP_DYNCOM_TABLE
1910DYNCOM_FILL_ACTION(vcvtbff),
1911#endif
1912#ifdef VFP_DYNCOM_TAG
1913int DYNCOM_TAG(vcvtbff)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1914{
1915 int instr_size = INSTR_SIZE;
1916 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1917 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1918 return instr_size;
1919}
1920#endif
1921#ifdef VFP_DYNCOM_TRANS
1922int DYNCOM_TRANS(vcvtbff)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1923 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1924 arch_arm_undef(cpu, bb, instr);
1925 return No_exp;
1926}
1927#endif
1928
1929/* ----------------------------------------------------------------------- */ 910/* ----------------------------------------------------------------------- */
1930/* VCVTBFI between floating point and integer */ 911/* VCVTBFI between floating point and integer */
1931/* cond 1110 1D11 1op2 Vd-- 101X X1M0 Vm-- */ 912/* cond 1110 1D11 1op2 Vd-- 101X X1M0 Vm-- */
@@ -1976,114 +957,6 @@ VCVTBFI_INST:
1976} 957}
1977#endif 958#endif
1978 959
1979#ifdef VFP_DYNCOM_TABLE
1980DYNCOM_FILL_ACTION(vcvtbfi),
1981#endif
1982#ifdef VFP_DYNCOM_TAG
1983int DYNCOM_TAG(vcvtbfi)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1984{
1985 int instr_size = INSTR_SIZE;
1986 LOG_TRACE(Core_ARM11, "\t\tin %s, instruction will be executed out of JIT.\n", __FUNCTION__);
1987 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1988 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1989 return instr_size;
1990}
1991#endif
1992#ifdef VFP_DYNCOM_TRANS
1993int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1994 LOG_TRACE(Core_ARM11, "\t\tin %s, instruction will be executed out of JIT.\n", __FUNCTION__);
1995 //arch_arm_undef(cpu, bb, instr);
1996 unsigned int opc2 = BITS(16,18);
1997 int to_integer = ((opc2 >> 2) == 1);
1998 int dp_op = (BIT(8) == 1);
1999 unsigned int op = BIT(7);
2000 int m,d;
2001 Value* v;
2002 Value* hi;
2003 Value* lo;
2004 Value* v64;
2005 if(to_integer){
2006 d = BIT(22) | (BITS(12,15) << 1);
2007 if(dp_op)
2008 m = BITS(0,3) | BIT(5) << 4;
2009 else
2010 m = BIT(5) | BITS(0,3) << 1;
2011 }else {
2012 m = BIT(5) | BITS(0,3) << 1;
2013 if(dp_op)
2014 d = BITS(12,15) | BIT(22) << 4;
2015 else
2016 d = BIT(22) | BITS(12,15) << 1;
2017 }
2018 if(to_integer){
2019 if(dp_op){
2020 lo = FR32(m * 2);
2021 hi = FR32(m * 2 + 1);
2022 hi = ZEXT64(IBITCAST32(hi));
2023 lo = ZEXT64(IBITCAST32(lo));
2024 v64 = OR(SHL(hi,CONST64(32)),lo);
2025 if(BIT(16)){
2026 v = FPTOSI(32,FPBITCAST64(v64));
2027 }
2028 else
2029 v = FPTOUI(32,FPBITCAST64(v64));
2030
2031 v = FPBITCAST32(v);
2032 LETFPS(d,v);
2033 }else {
2034 v = FR32(m);
2035 if(BIT(16)){
2036 v = FPTOSI(32,v);
2037 }
2038 else
2039 v = FPTOUI(32,v);
2040 LETFPS(d,FPBITCAST32(v));
2041 }
2042 }else {
2043 if(dp_op){
2044 v = IBITCAST32(FR32(m));
2045 if(BIT(7))
2046 v64 = SITOFP(64,v);
2047 else
2048 v64 = UITOFP(64,v);
2049 v = IBITCAST64(v64);
2050 hi = FPBITCAST32(TRUNC32(LSHR(v,CONST64(32))));
2051 lo = FPBITCAST32(TRUNC32(AND(v,CONST64(0xffffffff))));
2052 LETFPS(2 * d , lo);
2053 LETFPS(2 * d + 1, hi);
2054 }else {
2055 v = IBITCAST32(FR32(m));
2056 if(BIT(7))
2057 v = SITOFP(32,v);
2058 else
2059 v = UITOFP(32,v);
2060 LETFPS(d,v);
2061 }
2062 }
2063 return No_exp;
2064}
2065
2066/**
2067* @brief The implementation of c language for vcvtbfi instruction of dyncom
2068*
2069* @param cpu
2070* @param instr
2071*
2072* @return
2073*/
2074int vcvtbfi_instr_impl(arm_core_t* cpu, uint32 instr){
2075 int dp_operation = BIT(8);
2076 int ret;
2077 if (dp_operation)
2078 ret = vfp_double_cpdo(cpu, instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
2079 else
2080 ret = vfp_single_cpdo(cpu, instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
2081
2082 vfp_raise_exceptions(cpu, ret, instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
2083 return 0;
2084}
2085#endif
2086
2087/* ----------------------------------------------------------------------- */ 960/* ----------------------------------------------------------------------- */
2088/* MRC / MCR instructions */ 961/* MRC / MCR instructions */
2089/* cond 1110 AAAL XXXX XXXX 101C XBB1 XXXX */ 962/* cond 1110 AAAL XXXX XXXX 101C XBB1 XXXX */
@@ -2135,35 +1008,6 @@ VMOVBRS_INST:
2135} 1008}
2136#endif 1009#endif
2137 1010
2138#ifdef VFP_DYNCOM_TABLE
2139DYNCOM_FILL_ACTION(vmovbrs),
2140#endif
2141#ifdef VFP_DYNCOM_TAG
2142int DYNCOM_TAG(vmovbrs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2143{
2144 int instr_size = INSTR_SIZE;
2145 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2146 return instr_size;
2147}
2148#endif
2149#ifdef VFP_DYNCOM_TRANS
2150int DYNCOM_TRANS(vmovbrs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2151 int to_arm = BIT(20) == 1;
2152 int t = BITS(12, 15);
2153 int n = BIT(7) | BITS(16, 19)<<1;
2154
2155 if (to_arm)
2156 {
2157 LET(t, IBITCAST32(FR32(n)));
2158 }
2159 else
2160 {
2161 LETFPS(n, FPBITCAST32(R(t)));
2162 }
2163 return No_exp;
2164}
2165#endif
2166
2167/* ----------------------------------------------------------------------- */ 1011/* ----------------------------------------------------------------------- */
2168/* VMSR */ 1012/* VMSR */
2169/* cond 1110 1110 reg- Rt-- 1010 0001 0000 */ 1013/* cond 1110 1110 reg- Rt-- 1010 0001 0000 */
@@ -2211,48 +1055,6 @@ VMSR_INST:
2211} 1055}
2212#endif 1056#endif
2213 1057
2214#ifdef VFP_DYNCOM_TABLE
2215DYNCOM_FILL_ACTION(vmsr),
2216#endif
2217#ifdef VFP_DYNCOM_TAG
2218int DYNCOM_TAG(vmsr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2219{
2220 int instr_size = INSTR_SIZE;
2221 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
2222 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2223 return instr_size;
2224}
2225#endif
2226#ifdef VFP_DYNCOM_TRANS
2227int DYNCOM_TRANS(vmsr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2228 //arch_arm_undef(cpu, bb, instr);
2229 if(RD == 15) {
2230 LOG_ERROR(Core_ARM11, "in %s is not implementation.\n", __FUNCTION__);
2231 exit(-1);
2232 }
2233
2234 Value *data = NULL;
2235 int reg = RN;
2236 int Rt = RD;
2237 if (reg == 1)
2238 {
2239 LET(VFP_FPSCR, R(Rt));
2240 }
2241 else
2242 {
2243 switch (reg)
2244 {
2245 case 8:
2246 LET(VFP_FPEXC, R(Rt));
2247 break;
2248 default:
2249 break;
2250 }
2251 }
2252 return No_exp;
2253}
2254#endif
2255
2256/* ----------------------------------------------------------------------- */ 1058/* ----------------------------------------------------------------------- */
2257/* VMOVBRC register to scalar */ 1059/* VMOVBRC register to scalar */
2258/* cond 1110 0XX0 Vd-- Rt-- 1011 DXX1 0000 */ 1060/* cond 1110 0XX0 Vd-- Rt-- 1011 DXX1 0000 */
@@ -2302,26 +1104,6 @@ VMOVBRC_INST:
2302} 1104}
2303#endif 1105#endif
2304 1106
2305#ifdef VFP_DYNCOM_TABLE
2306DYNCOM_FILL_ACTION(vmovbrc),
2307#endif
2308#ifdef VFP_DYNCOM_TAG
2309int DYNCOM_TAG(vmovbrc)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2310{
2311 int instr_size = INSTR_SIZE;
2312 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2313 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
2314 return instr_size;
2315}
2316#endif
2317#ifdef VFP_DYNCOM_TRANS
2318int DYNCOM_TRANS(vmovbrc)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2319 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2320 arch_arm_undef(cpu, bb, instr);
2321 return No_exp;
2322}
2323#endif
2324
2325/* ----------------------------------------------------------------------- */ 1107/* ----------------------------------------------------------------------- */
2326/* VMRS */ 1108/* VMRS */
2327/* cond 1110 1111 CRn- Rt-- 1010 0001 0000 */ 1109/* cond 1110 1111 CRn- Rt-- 1010 0001 0000 */
@@ -2404,64 +1186,6 @@ VMRS_INST:
2404} 1186}
2405#endif 1187#endif
2406 1188
2407#ifdef VFP_DYNCOM_TABLE
2408DYNCOM_FILL_ACTION(vmrs),
2409#endif
2410#ifdef VFP_DYNCOM_TAG
2411int DYNCOM_TAG(vmrs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2412{
2413 int instr_size = INSTR_SIZE;
2414 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
2415 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2416 return instr_size;
2417}
2418#endif
2419#ifdef VFP_DYNCOM_TRANS
2420int DYNCOM_TRANS(vmrs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2421 //arch_arm_undef(cpu, bb, instr);
2422
2423 Value *data = NULL;
2424 int reg = BITS(16, 19);;
2425 int Rt = BITS(12, 15);
2426 if (reg == 1)
2427 {
2428 if (Rt != 15)
2429 {
2430 LET(Rt, R(VFP_FPSCR));
2431 }
2432 else
2433 {
2434 //LET(Rt, R(VFP_FPSCR));
2435 update_cond_from_fpscr(cpu, instr, bb, pc);
2436 }
2437 }
2438 else
2439 {
2440 switch (reg)
2441 {
2442 case 0:
2443 LET(Rt, R(VFP_FPSID));
2444 break;
2445 case 6:
2446 /* MVFR1, VFPv3 only ? */
2447 LOG_TRACE(Core_ARM11, "\tr%d <= MVFR1 unimplemented\n", Rt);
2448 break;
2449 case 7:
2450 /* MVFR0, VFPv3 only? */
2451 LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", Rt);
2452 break;
2453 case 8:
2454 LET(Rt, R(VFP_FPEXC));
2455 break;
2456 default:
2457 break;
2458 }
2459 }
2460
2461 return No_exp;
2462}
2463#endif
2464
2465/* ----------------------------------------------------------------------- */ 1189/* ----------------------------------------------------------------------- */
2466/* VMOVBCR scalar to register */ 1190/* VMOVBCR scalar to register */
2467/* cond 1110 XXX1 Vd-- Rt-- 1011 NXX1 0000 */ 1191/* cond 1110 XXX1 Vd-- Rt-- 1011 NXX1 0000 */
@@ -2511,26 +1235,6 @@ VMOVBCR_INST:
2511} 1235}
2512#endif 1236#endif
2513 1237
2514#ifdef VFP_DYNCOM_TABLE
2515DYNCOM_FILL_ACTION(vmovbcr),
2516#endif
2517#ifdef VFP_DYNCOM_TAG
2518int DYNCOM_TAG(vmovbcr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2519{
2520 int instr_size = INSTR_SIZE;
2521 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2522 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
2523 return instr_size;
2524}
2525#endif
2526#ifdef VFP_DYNCOM_TRANS
2527int DYNCOM_TRANS(vmovbcr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2528 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2529 arch_arm_undef(cpu, bb, instr);
2530 return No_exp;
2531}
2532#endif
2533
2534/* ----------------------------------------------------------------------- */ 1238/* ----------------------------------------------------------------------- */
2535/* MRRC / MCRR instructions */ 1239/* MRRC / MCRR instructions */
2536/* cond 1100 0101 Rt2- Rt-- copr opc1 CRm- MRRC */ 1240/* cond 1100 0101 Rt2- Rt-- copr opc1 CRm- MRRC */
@@ -2584,39 +1288,6 @@ VMOVBRRSS_INST:
2584 GOTO_NEXT_INST; 1288 GOTO_NEXT_INST;
2585} 1289}
2586#endif 1290#endif
2587#ifdef VFP_DYNCOM_TABLE
2588DYNCOM_FILL_ACTION(vmovbrrss),
2589#endif
2590#ifdef VFP_DYNCOM_TAG
2591int DYNCOM_TAG(vmovbrrss)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2592{
2593 int instr_size = INSTR_SIZE;
2594
2595 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2596 if (instr >> 28 != 0xE)
2597 *tag |= TAG_CONDITIONAL;
2598
2599 return instr_size;
2600}
2601#endif
2602#ifdef VFP_DYNCOM_TRANS
2603int DYNCOM_TRANS(vmovbrrss)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
2604{
2605 int to_arm = BIT(20) == 1;
2606 int t = BITS(12, 15);
2607 int t2 = BITS(16, 19);
2608 int n = BIT(5)<<4 | BITS(0, 3);
2609 if (to_arm) {
2610 LET(t, IBITCAST32(FR32(n + 0)));
2611 LET(t2, IBITCAST32(FR32(n + 1)));
2612 }
2613 else {
2614 LETFPS(n + 0, FPBITCAST32(R(t)));
2615 LETFPS(n + 1, FPBITCAST32(R(t2)));
2616 }
2617 return No_exp;
2618}
2619#endif
2620 1291
2621/* ----------------------------------------------------------------------- */ 1292/* ----------------------------------------------------------------------- */
2622/* VMOVBRRD between 2 registers and 1 double */ 1293/* VMOVBRRD between 2 registers and 1 double */
@@ -2667,38 +1338,6 @@ VMOVBRRD_INST:
2667} 1338}
2668#endif 1339#endif
2669 1340
2670#ifdef VFP_DYNCOM_TABLE
2671DYNCOM_FILL_ACTION(vmovbrrd),
2672#endif
2673#ifdef VFP_DYNCOM_TAG
2674int DYNCOM_TAG(vmovbrrd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2675{
2676 int instr_size = INSTR_SIZE;
2677 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2678 if(instr >> 28 != 0xe)
2679 *tag |= TAG_CONDITIONAL;
2680 return instr_size;
2681}
2682#endif
2683#ifdef VFP_DYNCOM_TRANS
2684int DYNCOM_TRANS(vmovbrrd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2685 //arch_arm_undef(cpu, bb, instr);
2686 int to_arm = BIT(20) == 1;
2687 int t = BITS(12, 15);
2688 int t2 = BITS(16, 19);
2689 int n = BIT(5)<<4 | BITS(0, 3);
2690 if(to_arm){
2691 LET(t, IBITCAST32(FR32(n * 2)));
2692 LET(t2, IBITCAST32(FR32(n * 2 + 1)));
2693 }
2694 else{
2695 LETFPS(n * 2, FPBITCAST32(R(t)));
2696 LETFPS(n * 2 + 1, FPBITCAST32(R(t2)));
2697 }
2698 return No_exp;
2699}
2700#endif
2701
2702/* ----------------------------------------------------------------------- */ 1341/* ----------------------------------------------------------------------- */
2703/* LDC/STC between 2 registers and 1 double */ 1342/* LDC/STC between 2 registers and 1 double */
2704/* cond 110X XXX1 Rn-- CRd- copr imm- imm- LDC */ 1343/* cond 110X XXX1 Rn-- CRd- copr imm- imm- LDC */
@@ -2764,53 +1403,6 @@ VSTR_INST:
2764} 1403}
2765#endif 1404#endif
2766 1405
2767#ifdef VFP_DYNCOM_TABLE
2768DYNCOM_FILL_ACTION(vstr),
2769#endif
2770#ifdef VFP_DYNCOM_TAG
2771int DYNCOM_TAG(vstr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2772{
2773 int instr_size = INSTR_SIZE;
2774 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2775 *tag |= TAG_NEW_BB;
2776 if(instr >> 28 != 0xe)
2777 *tag |= TAG_CONDITIONAL;
2778
2779 return instr_size;
2780}
2781#endif
2782#ifdef VFP_DYNCOM_TRANS
2783int DYNCOM_TRANS(vstr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2784 int single = BIT(8) == 0;
2785 int add = BIT(23);
2786 int imm32 = BITS(0,7) << 2;
2787 int d = (single ? BITS(12, 15)<<1|BIT(22) : BITS(12, 15)|(BIT(22)<<4));
2788 int n = BITS(16, 19);
2789
2790 Value* base = (n == 15) ? ADD(AND(R(n), CONST(0xFFFFFFFC)), CONST(8)): R(n);
2791 Value* Addr = add ? ADD(base, CONST(imm32)) : SUB(base, CONST(imm32));
2792 //if(single)
2793 // bb = arch_check_mm(cpu, bb, Addr, 4, 0, cpu->dyncom_engine->bb_trap);
2794 //else
2795 // bb = arch_check_mm(cpu, bb, Addr, 8, 0, cpu->dyncom_engine->bb_trap);
2796 //Value* phys_addr;
2797 if(single){
2798 //memory_write(cpu, bb, Addr, RSPR(d), 32);
2799 memory_write(cpu, bb, Addr, IBITCAST32(FR32(d)), 32);
2800 bb = cpu->dyncom_engine->bb;
2801 }
2802 else{
2803 //memory_write(cpu, bb, Addr, RSPR(d * 2), 32);
2804 memory_write(cpu, bb, Addr, IBITCAST32(FR32(d * 2)), 32);
2805 bb = cpu->dyncom_engine->bb;
2806 //memory_write(cpu, bb, ADD(Addr, CONST(4)), RSPR(d * 2 + 1), 32);
2807 memory_write(cpu, bb, ADD(Addr, CONST(4)), IBITCAST32(FR32(d * 2 + 1)), 32);
2808 bb = cpu->dyncom_engine->bb;
2809 }
2810 return No_exp;
2811}
2812#endif
2813
2814/* ----------------------------------------------------------------------- */ 1406/* ----------------------------------------------------------------------- */
2815/* VPUSH */ 1407/* VPUSH */
2816/* cond 1101 0D10 1101 Vd-- 101X imm8 imm8 */ 1408/* cond 1101 0D10 1101 Vd-- 101X imm8 imm8 */
@@ -2873,63 +1465,6 @@ VPUSH_INST:
2873 GOTO_NEXT_INST; 1465 GOTO_NEXT_INST;
2874} 1466}
2875#endif 1467#endif
2876#ifdef VFP_DYNCOM_TABLE
2877DYNCOM_FILL_ACTION(vpush),
2878#endif
2879#ifdef VFP_DYNCOM_TAG
2880int DYNCOM_TAG(vpush)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2881{
2882 int instr_size = INSTR_SIZE;
2883 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2884 *tag |= TAG_NEW_BB;
2885 if(instr >> 28 != 0xe)
2886 *tag |= TAG_CONDITIONAL;
2887
2888 return instr_size;
2889}
2890#endif
2891#ifdef VFP_DYNCOM_TRANS
2892int DYNCOM_TRANS(vpush)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2893 int single = BIT(8) == 0;
2894 int d = (single ? BITS(12, 15)<<1|BIT(22) : BITS(12, 15)|(BIT(22)<<4));
2895 int imm32 = BITS(0, 7)<<2;
2896 int regs = (single ? BITS(0, 7) : BITS(1, 7));
2897
2898 Value* Addr = SUB(R(13), CONST(imm32));
2899 //if(single)
2900 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 0, cpu->dyncom_engine->bb_trap);
2901 //else
2902 // bb = arch_check_mm(cpu, bb, Addr, regs * 8, 0, cpu->dyncom_engine->bb_trap);
2903 //Value* phys_addr;
2904
2905 for (int i = 0; i < regs; i++)
2906 {
2907 if (single)
2908 {
2909 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
2910 //memory_write(cpu, bb, Addr, RSPR(d + i), 32);
2911 memory_write(cpu, bb, Addr, IBITCAST32(FR32(d + i)), 32);
2912 bb = cpu->dyncom_engine->bb;
2913 Addr = ADD(Addr, CONST(4));
2914 }
2915 else
2916 {
2917 /* Careful of endianness, little by default */
2918 //memory_write(cpu, bb, Addr, RSPR((d + i) * 2), 32);
2919 memory_write(cpu, bb, Addr, IBITCAST32(FR32((d + i) * 2)), 32);
2920 bb = cpu->dyncom_engine->bb;
2921 //memory_write(cpu, bb, ADD(Addr, CONST(4)), RSPR((d + i) * 2 + 1), 32);
2922 memory_write(cpu, bb, ADD(Addr, CONST(4)), IBITCAST32(FR32((d + i) * 2 + 1)), 32);
2923 bb = cpu->dyncom_engine->bb;
2924
2925 Addr = ADD(Addr, CONST(8));
2926 }
2927 }
2928 LET(13, SUB(R(13), CONST(imm32)));
2929
2930 return No_exp;
2931}
2932#endif
2933 1468
2934/* ----------------------------------------------------------------------- */ 1469/* ----------------------------------------------------------------------- */
2935/* VSTM */ 1470/* VSTM */
@@ -3004,76 +1539,6 @@ VSTM_INST: /* encoding 1 */
3004} 1539}
3005#endif 1540#endif
3006 1541
3007#ifdef VFP_DYNCOM_TABLE
3008DYNCOM_FILL_ACTION(vstm),
3009#endif
3010#ifdef VFP_DYNCOM_TAG
3011int DYNCOM_TAG(vstm)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
3012{
3013 int instr_size = INSTR_SIZE;
3014 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
3015 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
3016 *tag |= TAG_NEW_BB;
3017 if(instr >> 28 != 0xe)
3018 *tag |= TAG_CONDITIONAL;
3019
3020 return instr_size;
3021}
3022#endif
3023#ifdef VFP_DYNCOM_TRANS
3024int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3025 //arch_arm_undef(cpu, bb, instr);
3026 int single = BIT(8) == 0;
3027 int add = BIT(23);
3028 int wback = BIT(21);
3029 int d = single ? BITS(12, 15)<<1|BIT(22) : BITS(12, 15)|(BIT(22)<<4);
3030 int n = BITS(16, 19);
3031 int imm32 = BITS(0, 7)<<2;
3032 int regs = single ? BITS(0, 7) : BITS(1, 7);
3033
3034 Value* Addr = SELECT(CONST1(add), R(n), SUB(R(n), CONST(imm32)));
3035 //if(single)
3036 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 0, cpu->dyncom_engine->bb_trap);
3037 //else
3038 // bb = arch_check_mm(cpu, bb, Addr, regs * 8, 0, cpu->dyncom_engine->bb_trap);
3039
3040 int i;
3041 Value* phys_addr;
3042 for (i = 0; i < regs; i++)
3043 {
3044 if (single)
3045 {
3046 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3047 /* if R(i) is R15? */
3048 //memory_write(cpu, bb, Addr, RSPR(d + i), 32);
3049 memory_write(cpu, bb, Addr, IBITCAST32(FR32(d + i)),32);
3050 bb = cpu->dyncom_engine->bb;
3051 Addr = ADD(Addr, CONST(4));
3052 }
3053 else
3054 {
3055 //Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
3056 //memory_write(cpu, bb, Addr, RSPR((d + i) * 2), 32);
3057 memory_write(cpu, bb, Addr, IBITCAST32(FR32((d + i) * 2)),32);
3058 bb = cpu->dyncom_engine->bb;
3059
3060 //Memory::Write32(addr + 4, cpu->ExtReg[(inst_cream->d+i)*2 + 1]);
3061 //memory_write(cpu, bb, ADD(Addr, CONST(4)), RSPR((d + i) * 2 + 1), 32);
3062 memory_write(cpu, bb, ADD(Addr, CONST(4)), IBITCAST32(FR32((d + i) * 2 + 1)), 32);
3063 bb = cpu->dyncom_engine->bb;
3064 //addr += 8;
3065 Addr = ADD(Addr, CONST(8));
3066 }
3067 }
3068 if (wback){
3069 //cpu->Reg[n] = (add ? cpu->Reg[n] + imm32 :
3070 // cpu->Reg[n] - imm32);
3071 LET(n, SELECT(CONST1(add), ADD(R(n), CONST(imm32)), SUB(R(n), CONST(imm32))));
3072 }
3073 return No_exp;
3074}
3075#endif
3076
3077/* ----------------------------------------------------------------------- */ 1542/* ----------------------------------------------------------------------- */
3078/* VPOP */ 1543/* VPOP */
3079/* cond 1100 1D11 1101 Vd-- 101X imm8 imm8 */ 1544/* cond 1100 1D11 1101 Vd-- 101X imm8 imm8 */
@@ -3142,70 +1607,6 @@ VPOP_INST:
3142} 1607}
3143#endif 1608#endif
3144 1609
3145#ifdef VFP_DYNCOM_TABLE
3146DYNCOM_FILL_ACTION(vpop),
3147#endif
3148#ifdef VFP_DYNCOM_TAG
3149int DYNCOM_TAG(vpop)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
3150{
3151 int instr_size = INSTR_SIZE;
3152 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
3153 /* Should check if PC is destination register */
3154 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
3155 *tag |= TAG_NEW_BB;
3156 if(instr >> 28 != 0xe)
3157 *tag |= TAG_CONDITIONAL;
3158
3159 return instr_size;
3160}
3161#endif
3162#ifdef VFP_DYNCOM_TRANS
3163int DYNCOM_TRANS(vpop)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3164 //arch_arm_undef(cpu, bb, instr);
3165 int single = BIT(8) == 0;
3166 int d = (single ? BITS(12, 15)<<1|BIT(22) : BITS(12, 15)|(BIT(22)<<4));
3167 int imm32 = BITS(0, 7)<<2;
3168 int regs = (single ? BITS(0, 7) : BITS(1, 7));
3169
3170 int i;
3171 unsigned int value1, value2;
3172
3173 Value* Addr = R(13);
3174 Value* val;
3175 //if(single)
3176 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap);
3177 //else
3178 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap);
3179 //Value* phys_addr;
3180 for (i = 0; i < regs; i++)
3181 {
3182 if (single)
3183 {
3184 memory_read(cpu, bb, Addr, 0, 32);
3185 bb = cpu->dyncom_engine->bb;
3186 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3187 LETFPS(d + i, FPBITCAST32(val));
3188 Addr = ADD(Addr, CONST(4));
3189 }
3190 else
3191 {
3192 /* Careful of endianness, little by default */
3193 memory_read(cpu, bb, Addr, 0, 32);
3194 bb = cpu->dyncom_engine->bb;
3195 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3196 LETFPS((d + i) * 2, FPBITCAST32(val));
3197 memory_read(cpu, bb, ADD(Addr, CONST(4)), 0, 32);
3198 bb = cpu->dyncom_engine->bb;
3199 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3200 LETFPS((d + i) * 2 + 1, FPBITCAST32(val));
3201
3202 Addr = ADD(Addr, CONST(8));
3203 }
3204 }
3205 LET(13, ADD(R(13), CONST(imm32)));
3206 return No_exp;
3207}
3208#endif
3209 1610
3210/* ----------------------------------------------------------------------- */ 1611/* ----------------------------------------------------------------------- */
3211/* VLDR */ 1612/* VLDR */
@@ -3271,67 +1672,6 @@ VLDR_INST:
3271} 1672}
3272#endif 1673#endif
3273 1674
3274#ifdef VFP_DYNCOM_TABLE
3275DYNCOM_FILL_ACTION(vldr),
3276#endif
3277#ifdef VFP_DYNCOM_TAG
3278int DYNCOM_TAG(vldr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
3279{
3280 int instr_size = INSTR_SIZE;
3281 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
3282 /* Should check if PC is destination register */
3283 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
3284 *tag |= TAG_NEW_BB;
3285 if(instr >> 28 != 0xe)
3286 *tag |= TAG_CONDITIONAL;
3287
3288 return instr_size;
3289}
3290#endif
3291#ifdef VFP_DYNCOM_TRANS
3292int DYNCOM_TRANS(vldr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3293 int single = BIT(8) == 0;
3294 int add = BIT(23);
3295 int wback = BIT(21);
3296 int d = (single ? BITS(12, 15)<<1|BIT(22) : BITS(12, 15)|(BIT(22)<<4));
3297 int n = BITS(16, 19);
3298 int imm32 = BITS(0, 7)<<2;
3299 int regs = (single ? BITS(0, 7) : BITS(1, 7));
3300 Value* base = R(n);
3301 if(n == 15){
3302 base = ADD(AND(base, CONST(0xFFFFFFFC)), CONST(8));
3303 }
3304 Value* Addr = add ? (ADD(base, CONST(imm32))) : (SUB(base, CONST(imm32)));
3305 //if(single)
3306 // bb = arch_check_mm(cpu, bb, Addr, 4, 1, cpu->dyncom_engine->bb_trap);
3307 //else
3308 // bb = arch_check_mm(cpu, bb, Addr, 8, 1, cpu->dyncom_engine->bb_trap);
3309 //Value* phys_addr;
3310 Value* val;
3311 if(single){
3312 memory_read(cpu, bb, Addr, 0, 32);
3313 bb = cpu->dyncom_engine->bb;
3314 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3315 //LETS(d, val);
3316 LETFPS(d,FPBITCAST32(val));
3317 }
3318 else{
3319 memory_read(cpu, bb, Addr, 0, 32);
3320 bb = cpu->dyncom_engine->bb;
3321 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3322 //LETS(d * 2, val);
3323 LETFPS(d * 2,FPBITCAST32(val));
3324 memory_read(cpu, bb, ADD(Addr, CONST(4)), 0,32);
3325 bb = cpu->dyncom_engine->bb;
3326 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3327 //LETS(d * 2 + 1, val);
3328 LETFPS( d * 2 + 1,FPBITCAST32(val));
3329 }
3330
3331 return No_exp;
3332}
3333#endif
3334
3335/* ----------------------------------------------------------------------- */ 1675/* ----------------------------------------------------------------------- */
3336/* VLDM */ 1676/* VLDM */
3337/* cond 110P UDW1 Rn-- Vd-- 101X imm8 imm8 */ 1677/* cond 110P UDW1 Rn-- Vd-- 101X imm8 imm8 */
@@ -3403,76 +1743,3 @@ VLDM_INST:
3403 GOTO_NEXT_INST; 1743 GOTO_NEXT_INST;
3404} 1744}
3405#endif 1745#endif
3406
3407#ifdef VFP_DYNCOM_TABLE
3408DYNCOM_FILL_ACTION(vldm),
3409#endif
3410#ifdef VFP_DYNCOM_TAG
3411int DYNCOM_TAG(vldm)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
3412{
3413 int instr_size = INSTR_SIZE;
3414 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
3415 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
3416 *tag |= TAG_NEW_BB;
3417 if(instr >> 28 != 0xe)
3418 *tag |= TAG_CONDITIONAL;
3419
3420 return instr_size;
3421}
3422#endif
3423#ifdef VFP_DYNCOM_TRANS
3424int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3425 int single = BIT(8) == 0;
3426 int add = BIT(23);
3427 int wback = BIT(21);
3428 int d = single ? BITS(12, 15)<<1|BIT(22) : BITS(12, 15)|BIT(22)<<4;
3429 int n = BITS(16, 19);
3430 int imm32 = BITS(0, 7)<<2;
3431 int regs = single ? BITS(0, 7) : BITS(1, 7);
3432
3433 Value* Addr = SELECT(CONST1(add), R(n), SUB(R(n), CONST(imm32)));
3434 //if(single)
3435 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap);
3436 //else
3437 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap);
3438
3439 int i;
3440 //Value* phys_addr;
3441 Value* val;
3442 for (i = 0; i < regs; i++)
3443 {
3444 if (single)
3445 {
3446 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3447 /* if R(i) is R15? */
3448 memory_read(cpu, bb, Addr, 0, 32);
3449 bb = cpu->dyncom_engine->bb;
3450 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3451 //LETS(d + i, val);
3452 LETFPS(d + i, FPBITCAST32(val));
3453 Addr = ADD(Addr, CONST(4));
3454 }
3455 else
3456 {
3457 memory_read(cpu, bb, Addr, 0, 32);
3458 bb = cpu->dyncom_engine->bb;
3459 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3460 LETFPS((d + i) * 2, FPBITCAST32(val));
3461 memory_read(cpu, bb, Addr, 0, 32);
3462 bb = cpu->dyncom_engine->bb;
3463 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3464 LETFPS((d + i) * 2 + 1, FPBITCAST32(val));
3465
3466 //Memory::Write(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
3467 //addr += 8;
3468 Addr = ADD(Addr, CONST(8));
3469 }
3470 }
3471 if (wback){
3472 //cpu->Reg[n] = (add ? cpu->Reg[n] + imm32 :
3473 // cpu->Reg[n] - imm32);
3474 LET(n, SELECT(CONST1(add), ADD(R(n), CONST(imm32)), SUB(R(n), CONST(imm32))));
3475 }
3476 return No_exp;
3477}
3478#endif
HIC SVNT DRACONES