GPU: Macros are specific to the Maxwell3D engine, so handle them internally.

8 files changed, 55 insertions, 63 deletions

diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index 26ba8c40b..1d578582e 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -64,35 +64,6 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value) {
     }
 }
 
-void GPU::CallMethod(u32 method, u32 subchannel, const std::vector<u32>& parameters) {
-    LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u num params %zu", method,
-                subchannel, parameters.size());
-
-    if (method < static_cast<u32>(BufferMethods::CountBufferMethods)) {
-        // TODO(Subv): Research and implement these methods.
-        LOG_ERROR(HW_GPU, "Special buffer methods other than Bind are not implemented");
-        return;
-    }
-
-    ASSERT(bound_engines.find(subchannel) != bound_engines.end());
-
-    const EngineID engine = bound_engines[subchannel];
-
-    switch (engine) {
-    case EngineID::FERMI_TWOD_A:
-        fermi_2d->CallMethod(method, parameters);
-        break;
-    case EngineID::MAXWELL_B:
-        maxwell_3d->CallMethod(method, parameters);
-        break;
-    case EngineID::MAXWELL_COMPUTE_B:
-        maxwell_compute->CallMethod(method, parameters);
-        break;
-    default:
-        UNIMPLEMENTED();
-    }
-}
-
 void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
     // TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an
     // application VAddr.
diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp
index 6c6162cf3..7aab163dc 100644
--- a/src/video_core/engines/fermi_2d.cpp
+++ b/src/video_core/engines/fermi_2d.cpp
@@ -8,7 +8,6 @@ namespace Tegra {
 namespace Engines {
 
 void Fermi2D::WriteReg(u32 method, u32 value) {}
-void Fermi2D::CallMethod(u32 method, const std::vector<u32>& parameters) {}
 
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index ce8920cee..8967ddede 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -4,7 +4,6 @@
 
 #pragma once
 
-#include <vector>
 #include "common/common_types.h"
 
 namespace Tegra {
@@ -17,13 +16,6 @@ public:
 
     /// Write the value to the register identified by method.
     void WriteReg(u32 method, u32 value);
-
-    /**
-     * Handles a method call to this engine.
-     * @param method Method to call
-     * @param parameters Arguments to the method call
-     */
-    void CallMethod(u32 method, const std::vector<u32>& parameters);
 };
 
 } // namespace Engines
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index db12fc702..67b1b4e7f 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -8,28 +8,59 @@
 namespace Tegra {
 namespace Engines {
 
+/// First register id that is actually a Macro call.
+constexpr u32 MacroRegistersStart = 0xE00;
+
 const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = {
     {0xE24, {"SetShader", 5, &Maxwell3D::SetShader}},
 };
 
 Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
 
-void Maxwell3D::CallMethod(u32 method, const std::vector<u32>& parameters) {
+void Maxwell3D::AttemptMethodCall(u32 method, const std::vector<u32>& parameters) {
     // TODO(Subv): Write an interpreter for the macros uploaded via registers 0x45 and 0x47
     auto itr = method_handlers.find(method);
-    if (itr == method_handlers.end()) {
-        LOG_ERROR(HW_GPU, "Unhandled method call %08X", method);
+    ASSERT_MSG(itr != method_handlers.end(), "Unhandled method call %08X", method);
+
+    // Only execute the macro handler once we've been fed the expected number of parameters.
+    if (itr->second.arguments != parameters.size())
         return;
-    }
 
-    ASSERT(itr->second.arguments == parameters.size());
     (this->*itr->second.handler)(parameters);
+
+    // Reset the current macro and its parameters.
+    executing_macro = 0;
+    macro_params.clear();
 }
 
 void Maxwell3D::WriteReg(u32 method, u32 value) {
     ASSERT_MSG(method < Regs::NUM_REGS,
                "Invalid Maxwell3D register, increase the size of the Regs structure");
 
+    // It is an error to write to a register other than the current macro's ARG register before it
+    // has finished execution.
+    if (executing_macro != 0) {
+        ASSERT(method == executing_macro + 1);
+    }
+
+    // Methods after 0xE00 are special, they're actually triggers for some microcode that was
+    // uploaded to the GPU during initialization.
+    if (method >= MacroRegistersStart) {
+        // We're trying to execute a macro
+        if (executing_macro == 0) {
+            // A macro call must begin by writing the macro method's register, not its argument.
+            ASSERT_MSG((method % 2) == 0,
+                       "Can't start macro execution by writing to the ARGS register");
+            executing_macro = method;
+        }
+
+        macro_params.push_back(value);
+
+        // Try to call the macro with the current number of parameters.
+        AttemptMethodCall(executing_macro, macro_params);
+        return;
+    }
+
     regs.reg_array[method] = value;
 
 #define MAXWELL3D_REG_INDEX(field_name) (offsetof(Regs, field_name) / sizeof(u32))
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 98137f94b..75a1c05bc 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -23,13 +23,6 @@ public:
     /// Write the value to the register identified by method.
     void WriteReg(u32 method, u32 value);
 
-    /**
-     * Handles a method call to this engine.
-     * @param method Method to call
-     * @param parameters Arguments to the method call
-     */
-    void CallMethod(u32 method, const std::vector<u32>& parameters);
-
     /// Register structure of the Maxwell3D engine.
     /// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
     struct Regs {
@@ -166,7 +159,11 @@ public:
                     INSERT_PADDING_WORDS(7);
                 } cb_bind[MaxShaderStage];
 
-                INSERT_PADDING_WORDS(0x50A);
+                INSERT_PADDING_WORDS(0x56);
+
+                u32 tex_cb_index;
+
+                INSERT_PADDING_WORDS(0x4B3);
             };
             std::array<u32, NUM_REGS> reg_array;
         };
@@ -201,6 +198,19 @@ public:
 private:
     MemoryManager& memory_manager;
 
+    /// Macro method that is currently being executed / being fed parameters.
+    u32 executing_macro = 0;
+    /// Parameters that have been submitted to the macro call so far.
+    std::vector<u32> macro_params;
+
+    /**
+     * Attempts a method call to this engine. Will return without doing anything if the number of
+     * parameters doesn't match what is expected for the method.
+     * @param method Method to call
+     * @param parameters Arguments to the method call
+     */
+    void AttemptMethodCall(u32 method, const std::vector<u32>& parameters);
+
     /// Handles a write to the QUERY_GET register.
     void ProcessQueryGet();
 
@@ -234,6 +244,7 @@ ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
 ASSERT_REG_POSITION(shader_config[0], 0x800);
 ASSERT_REG_POSITION(const_buffer, 0x8E0);
 ASSERT_REG_POSITION(cb_bind[0], 0x904);
+ASSERT_REG_POSITION(tex_cb_index, 0x982);
 
 #undef ASSERT_REG_POSITION
 
diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp
index 3bef7fe86..e4e5f9e5e 100644
--- a/src/video_core/engines/maxwell_compute.cpp
+++ b/src/video_core/engines/maxwell_compute.cpp
@@ -8,7 +8,6 @@ namespace Tegra {
 namespace Engines {
 
 void MaxwellCompute::WriteReg(u32 method, u32 value) {}
-void MaxwellCompute::CallMethod(u32 method, const std::vector<u32>& parameters) {}
 
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/maxwell_compute.h b/src/video_core/engines/maxwell_compute.h
index 5fc7ed635..7262e1bcb 100644
--- a/src/video_core/engines/maxwell_compute.h
+++ b/src/video_core/engines/maxwell_compute.h
@@ -4,7 +4,6 @@
 
 #pragma once
 
-#include <vector>
 #include "common/common_types.h"
 
 namespace Tegra {
@@ -17,13 +16,6 @@ public:
 
     /// Write the value to the register identified by method.
     void WriteReg(u32 method, u32 value);
-
-    /**
-     * Handles a method call to this engine.
-     * @param method Method to call
-     * @param parameters Arguments to the method call
-     */
-    void CallMethod(u32 method, const std::vector<u32>& parameters);
 };
 
 } // namespace Engines
diff --git a/src/video_core/gpu.h b/src/video_core/gpu.h
index c5ec6fdef..ba7781756 100644
--- a/src/video_core/gpu.h
+++ b/src/video_core/gpu.h
@@ -41,9 +41,6 @@ private:
     /// Writes a single register in the engine bound to the specified subchannel
     void WriteReg(u32 method, u32 subchannel, u32 value);
 
-    /// Calls a method in the engine bound to the specified subchannel with the input parameters.
-    void CallMethod(u32 method, u32 subchannel, const std::vector<u32>& parameters);
-
     /// Mapping of command subchannels to their bound engine ids.
     std::unordered_map<u32, EngineID> bound_engines;