shader/shift: Implement SHIFT_RIGHT_{IMM,R}

Shifts a pair of registers to the right and returns the low register.

1 files changed, 58 insertions, 26 deletions

diff --git a/src/video_core/shader/decode/shift.cpp b/src/video_core/shader/decode/shift.cpp
index 98e71b5f2..3b391d3e6 100644
--- a/src/video_core/shader/decode/shift.cpp
+++ b/src/video_core/shader/decode/shift.cpp
@@ -18,10 +18,14 @@ using Tegra::Shader::ShfXmode;
 
 namespace {
 
+Node IsFull(Node shift) {
+    return Operation(OperationCode::LogicalIEqual, move(shift), Immediate(32));
+}
+
 Node Shift(OperationCode opcode, Node value, Node shift) {
     Node is_full = Operation(OperationCode::LogicalIEqual, shift, Immediate(32));
-    Node shifted = Operation(opcode, move(value), move(shift));
-    return Operation(OperationCode::Select, move(is_full), Immediate(0), move(shifted));
+    Node shifted = Operation(opcode, move(value), shift);
+    return Operation(OperationCode::Select, IsFull(move(shift)), Immediate(0), move(shifted));
 }
 
 Node ClampShift(Node shift, s32 size = 32) {
@@ -33,6 +37,52 @@ Node WrapShift(Node shift, s32 size = 32) {
     return Operation(OperationCode::UBitwiseAnd, move(shift), Immediate(size - 1));
 }
 
+Node ShiftRight(Node low, Node high, Node shift, Node low_shift, ShfType type) {
+    // These values are used when the shift value is less than 32
+    Node less_low = Shift(OperationCode::ILogicalShiftRight, low, shift);
+    Node less_high = Shift(OperationCode::ILogicalShiftLeft, high, low_shift);
+    Node less = Operation(OperationCode::IBitwiseOr, move(less_high), move(less_low));
+
+    if (type == ShfType::Bits32) {
+        // On 32 bit shifts we are either full (shifting 32) or shifting less than 32 bits
+        return Operation(OperationCode::Select, IsFull(move(shift)), move(high), move(less));
+    }
+
+    // And these when it's larger than or 32
+    const bool is_signed = type == ShfType::S64;
+    const auto opcode = SignedToUnsignedCode(OperationCode::IArithmeticShiftRight, is_signed);
+    Node reduced = Operation(OperationCode::IAdd, shift, Immediate(-32));
+    Node greater = Shift(opcode, high, move(reduced));
+
+    Node is_less = Operation(OperationCode::LogicalILessThan, shift, Immediate(32));
+    Node is_zero = Operation(OperationCode::LogicalIEqual, move(shift), Immediate(0));
+
+    Node value = Operation(OperationCode::Select, move(is_less), move(less), move(greater));
+    return Operation(OperationCode::Select, move(is_zero), move(high), move(value));
+}
+
+Node ShiftLeft(Node low, Node high, Node shift, Node low_shift, ShfType type) {
+    // These values are used when the shift value is less than 32
+    Node less_low = Operation(OperationCode::ILogicalShiftRight, low, low_shift);
+    Node less_high = Operation(OperationCode::ILogicalShiftLeft, high, shift);
+    Node less = Operation(OperationCode::IBitwiseOr, move(less_low), move(less_high));
+
+    if (type == ShfType::Bits32) {
+        // On 32 bit shifts we are either full (shifting 32) or shifting less than 32 bits
+        return Operation(OperationCode::Select, IsFull(move(shift)), move(low), move(less));
+    }
+
+    // And these when it's larger than or 32
+    Node reduced = Operation(OperationCode::IAdd, shift, Immediate(-32));
+    Node greater = Shift(OperationCode::ILogicalShiftLeft, move(low), move(reduced));
+
+    Node is_less = Operation(OperationCode::LogicalILessThan, shift, Immediate(32));
+    Node is_zero = Operation(OperationCode::LogicalIEqual, move(shift), Immediate(0));
+
+    Node value = Operation(OperationCode::Select, move(is_less), move(less), move(greater));
+    return Operation(OperationCode::Select, move(is_zero), move(high), move(value));
+}
+
 } // Anonymous namespace
 
 u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
@@ -50,7 +100,7 @@ u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
         }
     }();
 
-    switch (opcode->get().GetId()) {
+    switch (const auto opid = opcode->get().GetId(); opid) {
     case OpCode::Id::SHR_C:
     case OpCode::Id::SHR_R:
     case OpCode::Id::SHR_IMM: {
@@ -70,6 +120,8 @@ u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
         SetRegister(bb, instr.gpr0, move(value));
         break;
     }
+    case OpCode::Id::SHF_RIGHT_R:
+    case OpCode::Id::SHF_RIGHT_IMM:
     case OpCode::Id::SHF_LEFT_R:
     case OpCode::Id::SHF_LEFT_IMM: {
         UNIMPLEMENTED_IF(instr.generates_cc);
@@ -85,29 +137,9 @@ u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
         Node negated_shift = Operation(OperationCode::INegate, shift);
         Node low_shift = Operation(OperationCode::IAdd, move(negated_shift), Immediate(32));
 
-        Node low = move(op_a);
-        Node high = GetRegister(instr.gpr39);
-        Node value;
-        if (instr.shf.type == ShfType::Bits32) {
-            high = Shift(OperationCode::ILogicalShiftLeft, move(high), move(shift));
-            low = Shift(OperationCode::ILogicalShiftRight, move(op_a), move(low_shift));
-            value = Operation(OperationCode::IBitwiseOr, move(high), move(low));
-        } else {
-            // These values are used when the shift value is less than 32
-            Node less_low = Operation(OperationCode::ILogicalShiftRight, low, low_shift);
-            Node less_high = Operation(OperationCode::ILogicalShiftLeft, high, shift);
-            Node less = Operation(OperationCode::IBitwiseOr, move(less_low), move(less_high));
-
-            // And these when it's larger than or 32
-            Node reduced = Operation(OperationCode::IAdd, shift, Immediate(-32));
-            Node greater = Shift(OperationCode::ILogicalShiftLeft, move(low), move(reduced));
-
-            Node is_less = Operation(OperationCode::LogicalILessThan, shift, Immediate(32));
-            Node is_zero = Operation(OperationCode::LogicalIEqual, move(shift), Immediate(0));
-
-            value = Operation(OperationCode::Select, move(is_less), move(less), move(greater));
-            value = Operation(OperationCode::Select, move(is_zero), move(high), move(value));
-        }
+        const bool is_right = opid == OpCode::Id::SHF_RIGHT_R || opid == OpCode::Id::SHF_RIGHT_IMM;
+        Node value = (is_right ? ShiftRight : ShiftLeft)(
+            move(op_a), GetRegister(instr.gpr39), move(shift), move(low_shift), instr.shf.type);
 
         SetRegister(bb, instr.gpr0, move(value));
         break;