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| author | 2018-09-01 19:05:10 +1000 | |
|---|---|---|
| committer | 2018-09-01 19:05:10 +1000 | |
| commit | 6f8ed9508dd1f7e104349bcf76acdf40da996e4c (patch) | |
| tree | 7dda05b50062ef7b5e8212dfc40168acecfae02c /src | |
| parent | Merge pull request #1196 from FearlessTobi/ccache-consistency (diff) | |
| download | yuzu-6f8ed9508dd1f7e104349bcf76acdf40da996e4c.tar.gz yuzu-6f8ed9508dd1f7e104349bcf76acdf40da996e4c.tar.xz yuzu-6f8ed9508dd1f7e104349bcf76acdf40da996e4c.zip | |
Added FMUL asserts
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 5 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 10 |
2 files changed, 15 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 3e4efbe0c..f07992131 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -332,7 +332,12 @@ union Instruction { | |||
| 332 | } ipa; | 332 | } ipa; |
| 333 | 333 | ||
| 334 | union { | 334 | union { |
| 335 | BitField<39, 2, u64> tab5cb8_2; | ||
| 336 | BitField<41, 3, u64> tab5c68_1; | ||
| 337 | BitField<44, 2, u64> tab5c68_0; | ||
| 338 | BitField<47, 1, u64> cc; | ||
| 335 | BitField<48, 1, u64> negate_b; | 339 | BitField<48, 1, u64> negate_b; |
| 340 | BitField<50, 1, u64> saturate; | ||
| 336 | } fmul; | 341 | } fmul; |
| 337 | 342 | ||
| 338 | union { | 343 | union { |
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 391c92d47..f33e8d70f 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -1038,6 +1038,16 @@ private: | |||
| 1038 | case OpCode::Id::FMUL_R: | 1038 | case OpCode::Id::FMUL_R: |
| 1039 | case OpCode::Id::FMUL_IMM: { | 1039 | case OpCode::Id::FMUL_IMM: { |
| 1040 | // FMUL does not have 'abs' bits and only the second operand has a 'neg' bit. | 1040 | // FMUL does not have 'abs' bits and only the second operand has a 'neg' bit. |
| 1041 | ASSERT_MSG(instr.fmul.tab5cb8_2 == 0, "FMUL tab5cb8_2({}) is not implemented", | ||
| 1042 | instr.fmul.tab5cb8_2.Value()); | ||
| 1043 | ASSERT_MSG(instr.fmul.tab5c68_1 == 0, "FMUL tab5cb8_1({}) is not implemented", | ||
| 1044 | instr.fmul.tab5c68_1.Value()); | ||
| 1045 | ASSERT_MSG(instr.fmul.tab5c68_0 == 1, "FMUL tab5cb8_0({}) is not implemented", | ||
| 1046 | instr.fmul.tab5c68_0 | ||
| 1047 | .Value()); // SMO typical sends 1 here which seems to be the default | ||
| 1048 | ASSERT_MSG(instr.fmul.cc == 0, "FMUL cc is not implemented"); | ||
| 1049 | ASSERT_MSG(instr.fmul.saturate == 0, "FMUL saturate is not implemented"); | ||
| 1050 | |||
| 1041 | op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b); | 1051 | op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b); |
| 1042 | regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1, | 1052 | regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1, |
| 1043 | instr.alu.saturate_d); | 1053 | instr.alu.saturate_d); |