diff options
| author | 2019-05-14 17:16:23 -0300 | |
|---|---|---|
| committer | 2019-07-19 22:20:47 -0300 | |
| commit | 6c4985edc9e05dbd9a93ba670625daee98c14bcf (patch) | |
| tree | 04fa84dcbc2401f09c6daf2db839bbd5df9f9ef2 /src | |
| parent | Merge pull request #2687 from lioncash/tls-process (diff) | |
| download | yuzu-6c4985edc9e05dbd9a93ba670625daee98c14bcf.tar.gz yuzu-6c4985edc9e05dbd9a93ba670625daee98c14bcf.tar.xz yuzu-6c4985edc9e05dbd9a93ba670625daee98c14bcf.zip | |
shader/half_set_predicate: Implement missing HSETP2 variants
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 26 | ||||
| -rw-r--r-- | src/video_core/shader/decode/half_set_predicate.cpp | 42 |
2 files changed, 49 insertions, 19 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 79d469b88..8520a0143 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -931,8 +931,6 @@ union Instruction { | |||
| 931 | } csetp; | 931 | } csetp; |
| 932 | 932 | ||
| 933 | union { | 933 | union { |
| 934 | BitField<35, 4, PredCondition> cond; | ||
| 935 | BitField<49, 1, u64> h_and; | ||
| 936 | BitField<6, 1, u64> ftz; | 934 | BitField<6, 1, u64> ftz; |
| 937 | BitField<45, 2, PredOperation> op; | 935 | BitField<45, 2, PredOperation> op; |
| 938 | BitField<3, 3, u64> pred3; | 936 | BitField<3, 3, u64> pred3; |
| @@ -940,9 +938,21 @@ union Instruction { | |||
| 940 | BitField<43, 1, u64> negate_a; | 938 | BitField<43, 1, u64> negate_a; |
| 941 | BitField<44, 1, u64> abs_a; | 939 | BitField<44, 1, u64> abs_a; |
| 942 | BitField<47, 2, HalfType> type_a; | 940 | BitField<47, 2, HalfType> type_a; |
| 943 | BitField<31, 1, u64> negate_b; | 941 | union { |
| 944 | BitField<30, 1, u64> abs_b; | 942 | BitField<35, 4, PredCondition> cond; |
| 945 | BitField<28, 2, HalfType> type_b; | 943 | BitField<49, 1, u64> h_and; |
| 944 | BitField<31, 1, u64> negate_b; | ||
| 945 | BitField<30, 1, u64> abs_b; | ||
| 946 | BitField<28, 2, HalfType> type_b; | ||
| 947 | } reg; | ||
| 948 | union { | ||
| 949 | BitField<56, 1, u64> negate_b; | ||
| 950 | BitField<54, 1, u64> abs_b; | ||
| 951 | } cbuf; | ||
| 952 | union { | ||
| 953 | BitField<49, 4, PredCondition> cond; | ||
| 954 | BitField<53, 1, u64> h_and; | ||
| 955 | } cbuf_and_imm; | ||
| 946 | BitField<42, 1, u64> neg_pred; | 956 | BitField<42, 1, u64> neg_pred; |
| 947 | BitField<39, 3, u64> pred39; | 957 | BitField<39, 3, u64> pred39; |
| 948 | } hsetp2; | 958 | } hsetp2; |
| @@ -1548,7 +1558,9 @@ public: | |||
| 1548 | HFMA2_RC, | 1558 | HFMA2_RC, |
| 1549 | HFMA2_RR, | 1559 | HFMA2_RR, |
| 1550 | HFMA2_IMM_R, | 1560 | HFMA2_IMM_R, |
| 1561 | HSETP2_C, | ||
| 1551 | HSETP2_R, | 1562 | HSETP2_R, |
| 1563 | HSETP2_IMM, | ||
| 1552 | HSET2_R, | 1564 | HSET2_R, |
| 1553 | POPC_C, | 1565 | POPC_C, |
| 1554 | POPC_R, | 1566 | POPC_R, |
| @@ -1831,7 +1843,9 @@ private: | |||
| 1831 | INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"), | 1843 | INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"), |
| 1832 | INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"), | 1844 | INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"), |
| 1833 | INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"), | 1845 | INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"), |
| 1834 | INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP_R"), | 1846 | INST("0111111-1-------", Id::HSETP2_C, Type::HalfSetPredicate, "HSETP2_C"), |
| 1847 | INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"), | ||
| 1848 | INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"), | ||
| 1835 | INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"), | 1849 | INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"), |
| 1836 | INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), | 1850 | INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), |
| 1837 | INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), | 1851 | INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), |
diff --git a/src/video_core/shader/decode/half_set_predicate.cpp b/src/video_core/shader/decode/half_set_predicate.cpp index d59d15bd8..ff41fb2b5 100644 --- a/src/video_core/shader/decode/half_set_predicate.cpp +++ b/src/video_core/shader/decode/half_set_predicate.cpp | |||
| @@ -23,17 +23,33 @@ u32 ShaderIR::DecodeHalfSetPredicate(NodeBlock& bb, u32 pc) { | |||
| 23 | Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a); | 23 | Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a); |
| 24 | op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a); | 24 | op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a); |
| 25 | 25 | ||
| 26 | Node op_b = [&]() { | 26 | Tegra::Shader::PredCondition cond{}; |
| 27 | switch (opcode->get().GetId()) { | 27 | bool h_and{}; |
| 28 | case OpCode::Id::HSETP2_R: | 28 | Node op_b{}; |
| 29 | return GetOperandAbsNegHalf(GetRegister(instr.gpr20), instr.hsetp2.abs_a, | 29 | switch (opcode->get().GetId()) { |
| 30 | instr.hsetp2.negate_b); | 30 | case OpCode::Id::HSETP2_C: |
| 31 | default: | 31 | cond = instr.hsetp2.cbuf_and_imm.cond; |
| 32 | UNREACHABLE(); | 32 | h_and = instr.hsetp2.cbuf_and_imm.h_and; |
| 33 | return Immediate(0); | 33 | op_b = GetOperandAbsNegHalf(GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset), |
| 34 | } | 34 | instr.hsetp2.cbuf.abs_b, instr.hsetp2.cbuf.negate_b); |
| 35 | }(); | 35 | break; |
| 36 | op_b = UnpackHalfFloat(op_b, instr.hsetp2.type_b); | 36 | case OpCode::Id::HSETP2_IMM: |
| 37 | cond = instr.hsetp2.cbuf_and_imm.cond; | ||
| 38 | h_and = instr.hsetp2.cbuf_and_imm.h_and; | ||
| 39 | op_b = UnpackHalfImmediate(instr, true); | ||
| 40 | break; | ||
| 41 | case OpCode::Id::HSETP2_R: | ||
| 42 | cond = instr.hsetp2.reg.cond; | ||
| 43 | h_and = instr.hsetp2.reg.h_and; | ||
| 44 | op_b = | ||
| 45 | UnpackHalfFloat(GetOperandAbsNegHalf(GetRegister(instr.gpr20), instr.hsetp2.reg.abs_b, | ||
| 46 | instr.hsetp2.reg.negate_b), | ||
| 47 | instr.hsetp2.reg.type_b); | ||
| 48 | break; | ||
| 49 | default: | ||
| 50 | UNREACHABLE(); | ||
| 51 | op_b = Immediate(0); | ||
| 52 | } | ||
| 37 | 53 | ||
| 38 | // We can't use the constant predicate as destination. | 54 | // We can't use the constant predicate as destination. |
| 39 | ASSERT(instr.hsetp2.pred3 != static_cast<u64>(Pred::UnusedIndex)); | 55 | ASSERT(instr.hsetp2.pred3 != static_cast<u64>(Pred::UnusedIndex)); |
| @@ -42,9 +58,9 @@ u32 ShaderIR::DecodeHalfSetPredicate(NodeBlock& bb, u32 pc) { | |||
| 42 | 58 | ||
| 43 | const OperationCode combiner = GetPredicateCombiner(instr.hsetp2.op); | 59 | const OperationCode combiner = GetPredicateCombiner(instr.hsetp2.op); |
| 44 | const OperationCode pair_combiner = | 60 | const OperationCode pair_combiner = |
| 45 | instr.hsetp2.h_and ? OperationCode::LogicalAll2 : OperationCode::LogicalAny2; | 61 | h_and ? OperationCode::LogicalAll2 : OperationCode::LogicalAny2; |
| 46 | 62 | ||
| 47 | const Node comparison = GetPredicateComparisonHalf(instr.hsetp2.cond, op_a, op_b); | 63 | const Node comparison = GetPredicateComparisonHalf(cond, op_a, op_b); |
| 48 | const Node first_pred = Operation(pair_combiner, comparison); | 64 | const Node first_pred = Operation(pair_combiner, comparison); |
| 49 | 65 | ||
| 50 | // Set the primary predicate to the result of Predicate OP SecondPredicate | 66 | // Set the primary predicate to the result of Predicate OP SecondPredicate |