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| author | 2018-08-20 18:42:36 -0500 | |
|---|---|---|
| committer | 2018-08-20 18:42:36 -0500 | |
| commit | 6bcdf37d4fe1f77c7a6757c5889fda780b549071 (patch) | |
| tree | a3bbef109e4f5b73efb869a3baba9292b8add3a2 /src | |
| parent | Merge pull request #1104 from Subv/instanced_arrays (diff) | |
| download | yuzu-6bcdf37d4fe1f77c7a6757c5889fda780b549071.tar.gz yuzu-6bcdf37d4fe1f77c7a6757c5889fda780b549071.tar.xz yuzu-6bcdf37d4fe1f77c7a6757c5889fda780b549071.zip | |
GPU: Added registers for the logicop functionality.
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/maxwell_3d.h | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index 3c869d3a1..d03bc1c0c 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h | |||
| @@ -311,6 +311,25 @@ public: | |||
| 311 | AlwaysOld = 8, | 311 | AlwaysOld = 8, |
| 312 | }; | 312 | }; |
| 313 | 313 | ||
| 314 | enum class LogicOperation : u32 { | ||
| 315 | Clear = 0x1500, | ||
| 316 | And = 0x1501, | ||
| 317 | AndReverse = 0x1502, | ||
| 318 | Copy = 0x1503, | ||
| 319 | AndInverted = 0x1504, | ||
| 320 | NoOp = 0x1505, | ||
| 321 | Xor = 0x1506, | ||
| 322 | Or = 0x1507, | ||
| 323 | Nor = 0x1508, | ||
| 324 | Equiv = 0x1509, | ||
| 325 | Invert = 0x150A, | ||
| 326 | OrReverse = 0x150B, | ||
| 327 | CopyInverted = 0x150C, | ||
| 328 | OrInverted = 0x150D, | ||
| 329 | Nand = 0x150E, | ||
| 330 | Set = 0x150F, | ||
| 331 | }; | ||
| 332 | |||
| 314 | struct Cull { | 333 | struct Cull { |
| 315 | enum class FrontFace : u32 { | 334 | enum class FrontFace : u32 { |
| 316 | ClockWise = 0x0900, | 335 | ClockWise = 0x0900, |
| @@ -695,7 +714,14 @@ public: | |||
| 695 | 714 | ||
| 696 | Cull cull; | 715 | Cull cull; |
| 697 | 716 | ||
| 698 | INSERT_PADDING_WORDS(0x2B); | 717 | INSERT_PADDING_WORDS(0x28); |
| 718 | |||
| 719 | struct { | ||
| 720 | u32 enable; | ||
| 721 | LogicOperation operation; | ||
| 722 | } logic_op; | ||
| 723 | |||
| 724 | INSERT_PADDING_WORDS(0x1); | ||
| 699 | 725 | ||
| 700 | union { | 726 | union { |
| 701 | u32 raw; | 727 | u32 raw; |
| @@ -942,6 +968,7 @@ ASSERT_REG_POSITION(draw, 0x585); | |||
| 942 | ASSERT_REG_POSITION(index_array, 0x5F2); | 968 | ASSERT_REG_POSITION(index_array, 0x5F2); |
| 943 | ASSERT_REG_POSITION(instanced_arrays, 0x620); | 969 | ASSERT_REG_POSITION(instanced_arrays, 0x620); |
| 944 | ASSERT_REG_POSITION(cull, 0x646); | 970 | ASSERT_REG_POSITION(cull, 0x646); |
| 971 | ASSERT_REG_POSITION(logic_op, 0x671); | ||
| 945 | ASSERT_REG_POSITION(clear_buffers, 0x674); | 972 | ASSERT_REG_POSITION(clear_buffers, 0x674); |
| 946 | ASSERT_REG_POSITION(query, 0x6C0); | 973 | ASSERT_REG_POSITION(query, 0x6C0); |
| 947 | ASSERT_REG_POSITION(vertex_array[0], 0x700); | 974 | ASSERT_REG_POSITION(vertex_array[0], 0x700); |