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authorGravatar ReinUsesLisp2018-12-20 22:58:33 -0300
committerGravatar ReinUsesLisp2019-01-15 17:54:49 -0300
commit60f044df566569d00106a7bce28110aaca9fa534 (patch)
treee3084b477057c9c8d32de5ea0a306bd07f811381 /src
parentshader_ir: Add integer helpers (diff)
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shader_ir: Add half float helpers
Diffstat (limited to 'src')
-rw-r--r--src/video_core/shader/shader_ir.cpp37
-rw-r--r--src/video_core/shader/shader_ir.h7
2 files changed, 44 insertions, 0 deletions
diff --git a/src/video_core/shader/shader_ir.cpp b/src/video_core/shader/shader_ir.cpp
index e4b81040d..5951bdc7b 100644
--- a/src/video_core/shader/shader_ir.cpp
+++ b/src/video_core/shader/shader_ir.cpp
@@ -175,6 +175,43 @@ Node ShaderIR::GetOperandAbsNegInteger(Node value, bool absolute, bool negate, b
175 return value; 175 return value;
176} 176}
177 177
178Node ShaderIR::UnpackHalfImmediate(Instruction instr, bool has_negation) {
179 const Node value = Immediate(instr.half_imm.PackImmediates());
180 if (!has_negation) {
181 return value;
182 }
183 const Node first_negate = GetPredicate(instr.half_imm.first_negate != 0);
184 const Node second_negate = GetPredicate(instr.half_imm.second_negate != 0);
185
186 return Operation(OperationCode::HNegate, HALF_NO_PRECISE, value, first_negate, second_negate);
187}
188
189Node ShaderIR::HalfMerge(Node dest, Node src, Tegra::Shader::HalfMerge merge) {
190 switch (merge) {
191 case Tegra::Shader::HalfMerge::H0_H1:
192 return src;
193 case Tegra::Shader::HalfMerge::F32:
194 return Operation(OperationCode::HMergeF32, src);
195 case Tegra::Shader::HalfMerge::Mrg_H0:
196 return Operation(OperationCode::HMergeH0, dest, src);
197 case Tegra::Shader::HalfMerge::Mrg_H1:
198 return Operation(OperationCode::HMergeH1, dest, src);
199 }
200 UNREACHABLE();
201 return src;
202}
203
204Node ShaderIR::GetOperandAbsNegHalf(Node value, bool absolute, bool negate) {
205 if (absolute) {
206 value = Operation(OperationCode::HAbsolute, HALF_NO_PRECISE, value);
207 }
208 if (negate) {
209 value = Operation(OperationCode::HNegate, HALF_NO_PRECISE, value, GetPredicate(true),
210 GetPredicate(true));
211 }
212 return value;
213}
214
178void ShaderIR::SetRegister(BasicBlock& bb, Register dest, Node src) { 215void ShaderIR::SetRegister(BasicBlock& bb, Register dest, Node src) {
179 bb.push_back(Operation(OperationCode::Assign, GetRegister(dest), src)); 216 bb.push_back(Operation(OperationCode::Assign, GetRegister(dest), src));
180} 217}
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h
index 84c016da6..f3b17d2eb 100644
--- a/src/video_core/shader/shader_ir.h
+++ b/src/video_core/shader/shader_ir.h
@@ -653,6 +653,13 @@ private:
653 /// Conditionally absolute/negated integer. Absolute is applied first 653 /// Conditionally absolute/negated integer. Absolute is applied first
654 Node GetOperandAbsNegInteger(Node value, bool absolute, bool negate, bool is_signed); 654 Node GetOperandAbsNegInteger(Node value, bool absolute, bool negate, bool is_signed);
655 655
656 /// Unpacks a half immediate from an instruction
657 Node UnpackHalfImmediate(Tegra::Shader::Instruction instr, bool has_negation);
658 /// Merges a half pair into another value
659 Node HalfMerge(Node dest, Node src, Tegra::Shader::HalfMerge merge);
660 /// Conditionally absolute/negated half float pair. Absolute is applied first
661 Node GetOperandAbsNegHalf(Node value, bool absolute, bool negate);
662
656 template <typename... T> 663 template <typename... T>
657 inline Node Operation(OperationCode code, const T*... operands) { 664 inline Node Operation(OperationCode code, const T*... operands) {
658 return StoreNode(OperationNode(code, operands...)); 665 return StoreNode(OperationNode(code, operands...));