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| author | 2016-03-09 02:30:13 -0500 | |
|---|---|---|
| committer | 2016-03-09 03:12:53 -0500 | |
| commit | 6085b419e51ea652ab030bd6a4ab3b89c993dd90 (patch) | |
| tree | 9779fcaa9952913ecec672f8a649be3a18ac0a4f /src | |
| parent | emitter: friend class OpArg with XEmitter (diff) | |
| download | yuzu-6085b419e51ea652ab030bd6a4ab3b89c993dd90.tar.gz yuzu-6085b419e51ea652ab030bd6a4ab3b89c993dd90.tar.xz yuzu-6085b419e51ea652ab030bd6a4ab3b89c993dd90.zip | |
emitter: constexpr-ify OpArg
Diffstat (limited to 'src')
| -rw-r--r-- | src/common/x64/emitter.h | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/src/common/x64/emitter.h b/src/common/x64/emitter.h index 0efc0d202..5e228f159 100644 --- a/src/common/x64/emitter.h +++ b/src/common/x64/emitter.h | |||
| @@ -159,34 +159,35 @@ struct OpArg | |||
| 159 | { | 159 | { |
| 160 | friend class XEmitter; | 160 | friend class XEmitter; |
| 161 | 161 | ||
| 162 | OpArg() {} // dummy op arg, used for storage | 162 | constexpr OpArg() = default; // dummy op arg, used for storage |
| 163 | OpArg(u64 _offset, int _scale, X64Reg rmReg = RAX, X64Reg scaledReg = RAX) | 163 | constexpr OpArg(u64 offset_, int scale_, X64Reg rmReg = RAX, X64Reg scaledReg = RAX) |
| 164 | : scale(static_cast<u8>(scale_)) | ||
| 165 | , offsetOrBaseReg(static_cast<u16>(rmReg)) | ||
| 166 | , indexReg(static_cast<u16>(scaledReg)) | ||
| 167 | , offset(offset_) | ||
| 164 | { | 168 | { |
| 165 | operandReg = 0; | ||
| 166 | scale = (u8)_scale; | ||
| 167 | offsetOrBaseReg = (u16)rmReg; | ||
| 168 | indexReg = (u16)scaledReg; | ||
| 169 | //if scale == 0 never mind offsetting | ||
| 170 | offset = _offset; | ||
| 171 | } | 169 | } |
| 172 | bool operator==(const OpArg &b) const | 170 | |
| 171 | constexpr bool operator==(const OpArg &b) const | ||
| 173 | { | 172 | { |
| 174 | return operandReg == b.operandReg && scale == b.scale && offsetOrBaseReg == b.offsetOrBaseReg && | 173 | return operandReg == b.operandReg && |
| 175 | indexReg == b.indexReg && offset == b.offset; | 174 | scale == b.scale && |
| 175 | offsetOrBaseReg == b.offsetOrBaseReg && | ||
| 176 | indexReg == b.indexReg && | ||
| 177 | offset == b.offset; | ||
| 176 | } | 178 | } |
| 179 | |||
| 177 | void WriteRex(XEmitter *emit, int opBits, int bits, int customOp = -1) const; | 180 | void WriteRex(XEmitter *emit, int opBits, int bits, int customOp = -1) const; |
| 178 | void WriteVex(XEmitter* emit, X64Reg regOp1, X64Reg regOp2, int L, int pp, int mmmmm, int W = 0) const; | 181 | void WriteVex(XEmitter* emit, X64Reg regOp1, X64Reg regOp2, int L, int pp, int mmmmm, int W = 0) const; |
| 179 | void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=INVALID_REG, bool warn_64bit_offset = true) const; | 182 | void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=INVALID_REG, bool warn_64bit_offset = true) const; |
| 180 | void WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg operandReg, int bits); | 183 | void WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg operandReg, int bits); |
| 181 | |||
| 182 | void WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &operand, int bits) const; | 184 | void WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &operand, int bits) const; |
| 183 | bool IsImm() const {return scale == SCALE_IMM8 || scale == SCALE_IMM16 || scale == SCALE_IMM32 || scale == SCALE_IMM64;} | 185 | |
| 184 | bool IsSimpleReg() const {return scale == SCALE_NONE;} | 186 | constexpr bool IsImm() const { return scale == SCALE_IMM8 || scale == SCALE_IMM16 || scale == SCALE_IMM32 || scale == SCALE_IMM64; } |
| 185 | bool IsSimpleReg(X64Reg reg) const | 187 | constexpr bool IsSimpleReg() const { return scale == SCALE_NONE; } |
| 188 | constexpr bool IsSimpleReg(X64Reg reg) const | ||
| 186 | { | 189 | { |
| 187 | if (!IsSimpleReg()) | 190 | return IsSimpleReg() && GetSimpleReg() == reg; |
| 188 | return false; | ||
| 189 | return GetSimpleReg() == reg; | ||
| 190 | } | 191 | } |
| 191 | 192 | ||
| 192 | bool CanDoOpWith(const OpArg &other) const | 193 | bool CanDoOpWith(const OpArg &other) const |
| @@ -218,16 +219,15 @@ struct OpArg | |||
| 218 | } | 219 | } |
| 219 | } | 220 | } |
| 220 | 221 | ||
| 221 | X64Reg GetSimpleReg() const | 222 | constexpr X64Reg GetSimpleReg() const |
| 222 | { | 223 | { |
| 223 | if (scale == SCALE_NONE) | 224 | return scale == SCALE_NONE |
| 224 | return (X64Reg)offsetOrBaseReg; | 225 | ? static_cast<X64Reg>(offsetOrBaseReg) |
| 225 | else | 226 | : INVALID_REG; |
| 226 | return INVALID_REG; | ||
| 227 | } | 227 | } |
| 228 | 228 | ||
| 229 | u32 GetImmValue() const { | 229 | constexpr u32 GetImmValue() const { |
| 230 | return (u32)offset; | 230 | return static_cast<u32>(offset); |
| 231 | } | 231 | } |
| 232 | 232 | ||
| 233 | // For loops. | 233 | // For loops. |
| @@ -236,11 +236,11 @@ struct OpArg | |||
| 236 | } | 236 | } |
| 237 | 237 | ||
| 238 | private: | 238 | private: |
| 239 | u8 scale; | 239 | u8 scale = 0; |
| 240 | u16 offsetOrBaseReg; | 240 | u16 offsetOrBaseReg = 0; |
| 241 | u16 indexReg; | 241 | u16 indexReg = 0; |
| 242 | u64 offset; // use RIP-relative as much as possible - 64-bit immediates are not available. | 242 | u64 offset = 0; // use RIP-relative as much as possible - 64-bit immediates are not available. |
| 243 | u16 operandReg; | 243 | u16 operandReg = 0; |
| 244 | }; | 244 | }; |
| 245 | 245 | ||
| 246 | inline OpArg M(const void *ptr) {return OpArg((u64)ptr, (int)SCALE_RIP);} | 246 | inline OpArg M(const void *ptr) {return OpArg((u64)ptr, (int)SCALE_RIP);} |