summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorGravatar David Marcec2018-09-01 19:33:32 +1000
committerGravatar David Marcec2018-09-01 19:33:32 +1000
commit60754b472888b9eb3f69f57978512503d61b3915 (patch)
tree07d0911746586cf987e7884e51534a391cdea6e3 /src
parentAdded FMUL asserts (diff)
downloadyuzu-60754b472888b9eb3f69f57978512503d61b3915.tar.gz
yuzu-60754b472888b9eb3f69f57978512503d61b3915.tar.xz
yuzu-60754b472888b9eb3f69f57978512503d61b3915.zip
Removed saturate assert
Unneeded as we already implement it
Diffstat (limited to 'src')
-rw-r--r--src/video_core/engines/shader_bytecode.h1
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index f07992131..c8052a612 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -337,7 +337,6 @@ union Instruction {
337 BitField<44, 2, u64> tab5c68_0; 337 BitField<44, 2, u64> tab5c68_0;
338 BitField<47, 1, u64> cc; 338 BitField<47, 1, u64> cc;
339 BitField<48, 1, u64> negate_b; 339 BitField<48, 1, u64> negate_b;
340 BitField<50, 1, u64> saturate;
341 } fmul; 340 } fmul;
342 341
343 union { 342 union {
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index f33e8d70f..866afc7b5 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -1046,7 +1046,6 @@ private:
1046 instr.fmul.tab5c68_0 1046 instr.fmul.tab5c68_0
1047 .Value()); // SMO typical sends 1 here which seems to be the default 1047 .Value()); // SMO typical sends 1 here which seems to be the default
1048 ASSERT_MSG(instr.fmul.cc == 0, "FMUL cc is not implemented"); 1048 ASSERT_MSG(instr.fmul.cc == 0, "FMUL cc is not implemented");
1049 ASSERT_MSG(instr.fmul.saturate == 0, "FMUL saturate is not implemented");
1050 1049
1051 op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b); 1050 op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b);
1052 regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1, 1051 regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1,