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| author | 2015-03-22 14:57:48 -0400 | |
|---|---|---|
| committer | 2015-03-22 14:57:48 -0400 | |
| commit | 5ac2a41f7248a9f2cfbb8ee6180bd4ad1df47ff5 (patch) | |
| tree | 5d1aa3262a55fb4b1ae5df33e6175b362d32edda /src | |
| parent | Merge pull request #659 from lioncash/setend (diff) | |
| parent | armmmu: Remove unnecessary enum values (diff) | |
| download | yuzu-5ac2a41f7248a9f2cfbb8ee6180bd4ad1df47ff5.tar.gz yuzu-5ac2a41f7248a9f2cfbb8ee6180bd4ad1df47ff5.tar.xz yuzu-5ac2a41f7248a9f2cfbb8ee6180bd4ad1df47ff5.zip | |
Merge pull request #669 from lioncash/cruft
armmmu: Remove unnecessary enum values
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/skyeye_common/armmmu.h | 50 |
1 files changed, 20 insertions, 30 deletions
diff --git a/src/core/arm/skyeye_common/armmmu.h b/src/core/arm/skyeye_common/armmmu.h index 0f9eadafa..22e564c3d 100644 --- a/src/core/arm/skyeye_common/armmmu.h +++ b/src/core/arm/skyeye_common/armmmu.h | |||
| @@ -26,36 +26,26 @@ | |||
| 26 | // Register numbers in the MMU | 26 | // Register numbers in the MMU |
| 27 | enum | 27 | enum |
| 28 | { | 28 | { |
| 29 | MMU_ID = 0, | 29 | MMU_ID = 0, |
| 30 | MMU_CONTROL = 1, | 30 | MMU_CONTROL = 1, |
| 31 | MMU_TRANSLATION_TABLE_BASE = 2, | 31 | MMU_TRANSLATION_TABLE_BASE = 2, |
| 32 | MMU_DOMAIN_ACCESS_CONTROL = 3, | 32 | MMU_DOMAIN_ACCESS_CONTROL = 3, |
| 33 | MMU_FAULT_STATUS = 5, | 33 | MMU_FAULT_STATUS = 5, |
| 34 | MMU_FAULT_ADDRESS = 6, | 34 | MMU_FAULT_ADDRESS = 6, |
| 35 | MMU_CACHE_OPS = 7, | 35 | MMU_CACHE_OPS = 7, |
| 36 | MMU_TLB_OPS = 8, | 36 | MMU_TLB_OPS = 8, |
| 37 | MMU_CACHE_LOCKDOWN = 9, | 37 | MMU_CACHE_LOCKDOWN = 9, |
| 38 | MMU_TLB_LOCKDOWN = 10, | 38 | MMU_TLB_LOCKDOWN = 10, |
| 39 | MMU_PID = 13, | 39 | MMU_PID = 13, |
| 40 | 40 | ||
| 41 | // MMU_V4 | 41 | // MMU_V4 |
| 42 | MMU_V4_CACHE_OPS = 7, | 42 | MMU_V4_CACHE_OPS = 7, |
| 43 | MMU_V4_TLB_OPS = 8, | 43 | MMU_V4_TLB_OPS = 8, |
| 44 | 44 | ||
| 45 | // MMU_V3 | 45 | // MMU_V3 |
| 46 | MMU_V3_FLUSH_TLB = 5, | 46 | MMU_V3_FLUSH_TLB = 5, |
| 47 | MMU_V3_FLUSH_TLB_ENTRY = 6, | 47 | MMU_V3_FLUSH_TLB_ENTRY = 6, |
| 48 | MMU_V3_FLUSH_CACHE = 7, | 48 | MMU_V3_FLUSH_CACHE = 7, |
| 49 | |||
| 50 | // MMU Intel SA-1100 | ||
| 51 | MMU_SA_RB_OPS = 9, | ||
| 52 | MMU_SA_DEBUG = 14, | ||
| 53 | MMU_SA_CP15_R15 = 15, | ||
| 54 | |||
| 55 | // Intel xscale CP15 | ||
| 56 | XSCALE_CP15_CACHE_TYPE = 0, | ||
| 57 | XSCALE_CP15_AUX_CONTROL = 1, | ||
| 58 | XSCALE_CP15_COPRO_ACCESS = 15, | ||
| 59 | }; | 49 | }; |
| 60 | 50 | ||
| 61 | // Reads data in big/little endian format based on the | 51 | // Reads data in big/little endian format based on the |