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authorGravatar Yuri Kunde Schlesner2017-02-08 23:46:00 -0800
committerGravatar Yuri Kunde Schlesner2017-02-09 00:04:25 -0800
commit553e672777433c99afb0376b963aa5955e4c076f (patch)
tree3d9976a48e9f01fa141f569370503a101aeea1e4 /src
parentVideoCore: Force enum sizes to u32 in LightingRegs (diff)
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VideoCore: Split u64 Pica reg unions into 2 separate u32 unions
This eliminates UB when aliasing it with the array of u32 regs, and is compatible with non-LE architectures.
Diffstat (limited to 'src')
-rw-r--r--src/video_core/regs_pipeline.h78
1 files changed, 42 insertions, 36 deletions
diff --git a/src/video_core/regs_pipeline.h b/src/video_core/regs_pipeline.h
index 5844a66ee..0a4ec6e1e 100644
--- a/src/video_core/regs_pipeline.h
+++ b/src/video_core/regs_pipeline.h
@@ -14,7 +14,7 @@
14namespace Pica { 14namespace Pica {
15 15
16struct PipelineRegs { 16struct PipelineRegs {
17 enum class VertexAttributeFormat : u64 { 17 enum class VertexAttributeFormat : u32 {
18 BYTE = 0, 18 BYTE = 0,
19 UBYTE = 1, 19 UBYTE = 1,
20 SHORT = 2, 20 SHORT = 2,
@@ -31,34 +31,37 @@ struct PipelineRegs {
31 // Descriptor for internal vertex attributes 31 // Descriptor for internal vertex attributes
32 union { 32 union {
33 BitField<0, 2, VertexAttributeFormat> format0; // size of one element 33 BitField<0, 2, VertexAttributeFormat> format0; // size of one element
34 BitField<2, 2, u64> size0; // number of elements minus 1 34 BitField<2, 2, u32> size0; // number of elements minus 1
35 BitField<4, 2, VertexAttributeFormat> format1; 35 BitField<4, 2, VertexAttributeFormat> format1;
36 BitField<6, 2, u64> size1; 36 BitField<6, 2, u32> size1;
37 BitField<8, 2, VertexAttributeFormat> format2; 37 BitField<8, 2, VertexAttributeFormat> format2;
38 BitField<10, 2, u64> size2; 38 BitField<10, 2, u32> size2;
39 BitField<12, 2, VertexAttributeFormat> format3; 39 BitField<12, 2, VertexAttributeFormat> format3;
40 BitField<14, 2, u64> size3; 40 BitField<14, 2, u32> size3;
41 BitField<16, 2, VertexAttributeFormat> format4; 41 BitField<16, 2, VertexAttributeFormat> format4;
42 BitField<18, 2, u64> size4; 42 BitField<18, 2, u32> size4;
43 BitField<20, 2, VertexAttributeFormat> format5; 43 BitField<20, 2, VertexAttributeFormat> format5;
44 BitField<22, 2, u64> size5; 44 BitField<22, 2, u32> size5;
45 BitField<24, 2, VertexAttributeFormat> format6; 45 BitField<24, 2, VertexAttributeFormat> format6;
46 BitField<26, 2, u64> size6; 46 BitField<26, 2, u32> size6;
47 BitField<28, 2, VertexAttributeFormat> format7; 47 BitField<28, 2, VertexAttributeFormat> format7;
48 BitField<30, 2, u64> size7; 48 BitField<30, 2, u32> size7;
49 BitField<32, 2, VertexAttributeFormat> format8; 49 };
50 BitField<34, 2, u64> size8; 50
51 BitField<36, 2, VertexAttributeFormat> format9; 51 union {
52 BitField<38, 2, u64> size9; 52 BitField<0, 2, VertexAttributeFormat> format8;
53 BitField<40, 2, VertexAttributeFormat> format10; 53 BitField<2, 2, u32> size8;
54 BitField<42, 2, u64> size10; 54 BitField<4, 2, VertexAttributeFormat> format9;
55 BitField<44, 2, VertexAttributeFormat> format11; 55 BitField<6, 2, u32> size9;
56 BitField<46, 2, u64> size11; 56 BitField<8, 2, VertexAttributeFormat> format10;
57 57 BitField<10, 2, u32> size10;
58 BitField<48, 12, u64> attribute_mask; 58 BitField<12, 2, VertexAttributeFormat> format11;
59 BitField<14, 2, u32> size11;
60
61 BitField<16, 12, u32> attribute_mask;
59 62
60 // number of total attributes minus 1 63 // number of total attributes minus 1
61 BitField<60, 4, u64> max_attribute_index; 64 BitField<28, 4, u32> max_attribute_index;
62 }; 65 };
63 66
64 inline VertexAttributeFormat GetFormat(int n) const { 67 inline VertexAttributeFormat GetFormat(int n) const {
@@ -69,7 +72,7 @@ struct PipelineRegs {
69 } 72 }
70 73
71 inline int GetNumElements(int n) const { 74 inline int GetNumElements(int n) const {
72 u64 sizes[] = {size0, size1, size2, size3, size4, size5, 75 u32 sizes[] = {size0, size1, size2, size3, size4, size5,
73 size6, size7, size8, size9, size10, size11}; 76 size6, size7, size8, size9, size10, size11};
74 return (int)sizes[n] + 1; 77 return (int)sizes[n] + 1;
75 } 78 }
@@ -99,27 +102,30 @@ struct PipelineRegs {
99 u32 data_offset; 102 u32 data_offset;
100 103
101 union { 104 union {
102 BitField<0, 4, u64> comp0; 105 BitField<0, 4, u32> comp0;
103 BitField<4, 4, u64> comp1; 106 BitField<4, 4, u32> comp1;
104 BitField<8, 4, u64> comp2; 107 BitField<8, 4, u32> comp2;
105 BitField<12, 4, u64> comp3; 108 BitField<12, 4, u32> comp3;
106 BitField<16, 4, u64> comp4; 109 BitField<16, 4, u32> comp4;
107 BitField<20, 4, u64> comp5; 110 BitField<20, 4, u32> comp5;
108 BitField<24, 4, u64> comp6; 111 BitField<24, 4, u32> comp6;
109 BitField<28, 4, u64> comp7; 112 BitField<28, 4, u32> comp7;
110 BitField<32, 4, u64> comp8; 113 };
111 BitField<36, 4, u64> comp9; 114
112 BitField<40, 4, u64> comp10; 115 union {
113 BitField<44, 4, u64> comp11; 116 BitField<0, 4, u32> comp8;
117 BitField<4, 4, u32> comp9;
118 BitField<8, 4, u32> comp10;
119 BitField<12, 4, u32> comp11;
114 120
115 // bytes for a single vertex in this loader 121 // bytes for a single vertex in this loader
116 BitField<48, 8, u64> byte_count; 122 BitField<16, 8, u32> byte_count;
117 123
118 BitField<60, 4, u64> component_count; 124 BitField<28, 4, u32> component_count;
119 }; 125 };
120 126
121 inline int GetComponent(int n) const { 127 inline int GetComponent(int n) const {
122 u64 components[] = {comp0, comp1, comp2, comp3, comp4, comp5, 128 u32 components[] = {comp0, comp1, comp2, comp3, comp4, comp5,
123 comp6, comp7, comp8, comp9, comp10, comp11}; 129 comp6, comp7, comp8, comp9, comp10, comp11};
124 return (int)components[n]; 130 return (int)components[n];
125 } 131 }