summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorGravatar Lioncash2015-01-07 00:53:56 -0500
committerGravatar Lioncash2015-01-07 00:53:56 -0500
commit511e13f3e3d02da2ae8cccf7deb176b4c9c9f76b (patch)
tree7b9f9eef6ae9c7dbf0094ae10efe67594526a214 /src
parentMerge pull request #402 from chrisvj/master (diff)
downloadyuzu-511e13f3e3d02da2ae8cccf7deb176b4c9c9f76b.tar.gz
yuzu-511e13f3e3d02da2ae8cccf7deb176b4c9c9f76b.tar.xz
yuzu-511e13f3e3d02da2ae8cccf7deb176b4c9c9f76b.zip
dyncom: Move over SMLALXY
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp57
1 files changed, 56 insertions, 1 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 9b291862c..64264fac8 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -947,6 +947,15 @@ typedef struct _smla_inst {
947 unsigned int Rn; 947 unsigned int Rn;
948} smla_inst; 948} smla_inst;
949 949
950typedef struct smlalxy_inst {
951 unsigned int x;
952 unsigned int y;
953 unsigned int RdLo;
954 unsigned int RdHi;
955 unsigned int Rm;
956 unsigned int Rn;
957} smlalxy_inst;
958
950typedef struct ssat_inst { 959typedef struct ssat_inst {
951 unsigned int Rn; 960 unsigned int Rn;
952 unsigned int Rd; 961 unsigned int Rd;
@@ -2403,7 +2412,25 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index)
2403 return inst_base; 2412 return inst_base;
2404} 2413}
2405 2414
2406ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALXY"); } 2415ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index)
2416{
2417 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlalxy_inst));
2418 smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component;
2419
2420 inst_base->cond = BITS(inst, 28, 31);
2421 inst_base->idx = index;
2422 inst_base->br = NON_BRANCH;
2423 inst_base->load_r15 = 0;
2424
2425 inst_cream->x = BIT(inst, 5);
2426 inst_cream->y = BIT(inst, 6);
2427 inst_cream->RdLo = BITS(inst, 12, 15);
2428 inst_cream->RdHi = BITS(inst, 16, 19);
2429 inst_cream->Rn = BITS(inst, 0, 4);
2430 inst_cream->Rm = BITS(inst, 8, 11);
2431
2432 return inst_base;
2433}
2407 2434
2408ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) 2435ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index)
2409{ 2436{
@@ -5686,6 +5713,34 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5686 } 5713 }
5687 5714
5688 SMLALXY_INST: 5715 SMLALXY_INST:
5716 {
5717 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
5718 smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component;
5719
5720 u64 operand1 = RN;
5721 u64 operand2 = RM;
5722
5723 if (inst_cream->x != 0)
5724 operand1 >>= 16;
5725 if (inst_cream->y != 0)
5726 operand2 >>= 16;
5727 operand1 &= 0xFFFF;
5728 if (operand1 & 0x8000)
5729 operand1 -= 65536;
5730 operand2 &= 0xFFFF;
5731 if (operand2 & 0x8000)
5732 operand2 -= 65536;
5733
5734 u64 dest = ((u64)RDHI << 32 | RDLO) + (operand1 * operand2);
5735 RDLO = (dest & 0xFFFFFFFF);
5736 RDHI = ((dest >> 32) & 0xFFFFFFFF);
5737 }
5738
5739 cpu->Reg[15] += GET_INST_SIZE(cpu);
5740 INC_PC(sizeof(smlalxy_inst));
5741 FETCH_INST;
5742 GOTO_NEXT_INST;
5743 }
5689 5744
5690 SMLAW_INST: 5745 SMLAW_INST:
5691 { 5746 {