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authorGravatar MerryMage2016-08-14 00:49:34 +0100
committerGravatar MerryMage2016-08-14 00:49:34 +0100
commit50407a8dc86685d6f261680162823dfc44377285 (patch)
tree75f19adc5a46334a3794221dabc8624b3bb6ceeb /src
parentMerge pull request #1936 from jroweboy/qt5.7-fix (diff)
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Dyncom: Correct implementation of STM for R15
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 01d5d478e..6d5fb7aec 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3228,7 +3228,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
3228 addr += 4; 3228 addr += 4;
3229 } 3229 }
3230 if (BIT(inst_cream->inst, 15)) { 3230 if (BIT(inst_cream->inst, 15)) {
3231 cpu->WriteMemory32(addr, cpu->Reg_usr[1] + 8); 3231 cpu->WriteMemory32(addr, cpu->Reg[15] + 8);
3232 } 3232 }
3233 } else { 3233 } else {
3234 for (int i = 0; i < 15; i++) { 3234 for (int i = 0; i < 15; i++) {
@@ -3243,8 +3243,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
3243 } 3243 }
3244 3244
3245 // Check PC reg 3245 // Check PC reg
3246 if (BIT(inst_cream->inst, 15)) 3246 if (BIT(inst_cream->inst, 15)) {
3247 cpu->WriteMemory32(addr, cpu->Reg_usr[1] + 8); 3247 cpu->WriteMemory32(addr, cpu->Reg[15] + 8);
3248 }
3248 } 3249 }
3249 } 3250 }
3250 cpu->Reg[15] += cpu->GetInstructionSize(); 3251 cpu->Reg[15] += cpu->GetInstructionSize();