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authorGravatar ReinUsesLisp2018-12-26 03:18:11 -0300
committerGravatar ReinUsesLisp2019-01-15 17:54:53 -0300
commit50195b1704bcdf22d379d31b143172a32ebdfaec (patch)
tree27ec92fffda49be2aafaf2383a8a3999b40cff8c /src
parentshader_decode: Use BitfieldExtract instead of shift + and (diff)
downloadyuzu-50195b1704bcdf22d379d31b143172a32ebdfaec.tar.gz
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shader_decode: Use proper primitive names
Diffstat (limited to 'src')
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp18
-rw-r--r--src/video_core/shader/decode/memory.cpp4
-rw-r--r--src/video_core/shader/decode/other.cpp12
-rw-r--r--src/video_core/shader/shader_ir.h12
4 files changed, 21 insertions, 25 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 60b11df51..ceb54ec2c 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -325,8 +325,8 @@ private:
325 } 325 }
326 326
327 ASSERT(element.second.size() > 0); 327 ASSERT(element.second.size() > 0);
328 // UNIMPLEMENTED_IF_MSG(element.second.size() > 1, 328 UNIMPLEMENTED_IF_MSG(element.second.size() > 1,
329 // "Multiple input flag modes are not supported in GLSL"); 329 "Multiple input flag modes are not supported in GLSL");
330 330
331 // TODO(bunnei): Use proper number of elements for these 331 // TODO(bunnei): Use proper number of elements for these
332 u32 idx = static_cast<u32>(index) - static_cast<u32>(Attribute::Index::Attribute_0); 332 u32 idx = static_cast<u32>(index) - static_cast<u32>(Attribute::Index::Attribute_0);
@@ -1209,7 +1209,7 @@ private:
1209 return expr; 1209 return expr;
1210 } 1210 }
1211 1211
1212 std::string Bra(Operation operation) { 1212 std::string Branch(Operation operation) {
1213 const auto target = std::get<ImmediateNode>(*operation[0]); 1213 const auto target = std::get<ImmediateNode>(*operation[0]);
1214 code.AddLine(fmt::format("jmp_to = 0x{:x}u;", target.GetValue())); 1214 code.AddLine(fmt::format("jmp_to = 0x{:x}u;", target.GetValue()));
1215 code.AddLine("break;"); 1215 code.AddLine("break;");
@@ -1289,7 +1289,7 @@ private:
1289 return {}; 1289 return {};
1290 } 1290 }
1291 1291
1292 std::string Kil(Operation operation) { 1292 std::string Discard(Operation operation) {
1293 // Enclose "discard" in a conditional, so that GLSL compilation does not complain 1293 // Enclose "discard" in a conditional, so that GLSL compilation does not complain
1294 // about unexecuted instructions that may follow this. 1294 // about unexecuted instructions that may follow this.
1295 code.AddLine("if (true) {"); 1295 code.AddLine("if (true) {");
@@ -1449,13 +1449,11 @@ private:
1449 &GLSLDecompiler::F4TextureQueryLod, 1449 &GLSLDecompiler::F4TextureQueryLod,
1450 &GLSLDecompiler::F4TexelFetch, 1450 &GLSLDecompiler::F4TexelFetch,
1451 1451
1452 &GLSLDecompiler::Bra, 1452 &GLSLDecompiler::Branch,
1453 &GLSLDecompiler::PushFlowStack, // Ssy 1453 &GLSLDecompiler::PushFlowStack,
1454 &GLSLDecompiler::PushFlowStack, // Brk 1454 &GLSLDecompiler::PopFlowStack,
1455 &GLSLDecompiler::PopFlowStack, // Sync
1456 &GLSLDecompiler::PopFlowStack, // Brk
1457 &GLSLDecompiler::Exit, 1455 &GLSLDecompiler::Exit,
1458 &GLSLDecompiler::Kil, 1456 &GLSLDecompiler::Discard,
1459 1457
1460 &GLSLDecompiler::EmitVertex, 1458 &GLSLDecompiler::EmitVertex,
1461 &GLSLDecompiler::EndPrimitive, 1459 &GLSLDecompiler::EndPrimitive,
diff --git a/src/video_core/shader/decode/memory.cpp b/src/video_core/shader/decode/memory.cpp
index 60bdd9b73..f3f78a662 100644
--- a/src/video_core/shader/decode/memory.cpp
+++ b/src/video_core/shader/decode/memory.cpp
@@ -155,8 +155,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
155 break; 155 break;
156 } 156 }
157 case OpCode::Id::ST_L: { 157 case OpCode::Id::ST_L: {
158 // UNIMPLEMENTED_IF_MSG(instr.st_l.unknown == 0, "ST_L Unhandled mode: {}", 158 UNIMPLEMENTED_IF_MSG(instr.st_l.unknown == 0, "ST_L Unhandled mode: {}",
159 // static_cast<u32>(instr.st_l.unknown.Value())); 159 static_cast<u32>(instr.st_l.unknown.Value()));
160 160
161 const Node index = Operation(OperationCode::IAdd, NO_PRECISE, GetRegister(instr.gpr8), 161 const Node index = Operation(OperationCode::IAdd, NO_PRECISE, GetRegister(instr.gpr8),
162 Immediate(static_cast<s32>(instr.smem_imm))); 162 Immediate(static_cast<s32>(instr.smem_imm)));
diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp
index 386433d8e..6e6795ba7 100644
--- a/src/video_core/shader/decode/other.cpp
+++ b/src/video_core/shader/decode/other.cpp
@@ -54,7 +54,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
54 UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "KIL condition code used: {}", 54 UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "KIL condition code used: {}",
55 static_cast<u32>(cc)); 55 static_cast<u32>(cc));
56 56
57 bb.push_back(Operation(OperationCode::Kil)); 57 bb.push_back(Operation(OperationCode::Discard));
58 break; 58 break;
59 } 59 }
60 case OpCode::Id::MOV_SYS: { 60 case OpCode::Id::MOV_SYS: {
@@ -79,7 +79,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
79 "BRA with constant buffers are not implemented"); 79 "BRA with constant buffers are not implemented");
80 80
81 const u32 target = pc + instr.bra.GetBranchTarget(); 81 const u32 target = pc + instr.bra.GetBranchTarget();
82 const Node branch = Operation(OperationCode::Bra, Immediate(target)); 82 const Node branch = Operation(OperationCode::Branch, Immediate(target));
83 83
84 const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; 84 const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
85 if (cc != Tegra::Shader::ConditionCode::T) { 85 if (cc != Tegra::Shader::ConditionCode::T) {
@@ -97,7 +97,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
97 // target of the jump that the SYNC instruction will make. The SSY opcode has a similar 97 // target of the jump that the SYNC instruction will make. The SSY opcode has a similar
98 // structure to the BRA opcode. 98 // structure to the BRA opcode.
99 const u32 target = pc + instr.bra.GetBranchTarget(); 99 const u32 target = pc + instr.bra.GetBranchTarget();
100 bb.push_back(Operation(OperationCode::Ssy, Immediate(target))); 100 bb.push_back(Operation(OperationCode::PushFlowStack, Immediate(target)));
101 break; 101 break;
102 } 102 }
103 case OpCode::Id::PBK: { 103 case OpCode::Id::PBK: {
@@ -108,7 +108,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
108 // using SYNC on a PBK address will kill the shader execution. We don't emulate this because 108 // using SYNC on a PBK address will kill the shader execution. We don't emulate this because
109 // it's very unlikely a driver will emit such invalid shader. 109 // it's very unlikely a driver will emit such invalid shader.
110 const u32 target = pc + instr.bra.GetBranchTarget(); 110 const u32 target = pc + instr.bra.GetBranchTarget();
111 bb.push_back(Operation(OperationCode::Pbk, Immediate(target))); 111 bb.push_back(Operation(OperationCode::PushFlowStack, Immediate(target)));
112 break; 112 break;
113 } 113 }
114 case OpCode::Id::SYNC: { 114 case OpCode::Id::SYNC: {
@@ -117,7 +117,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
117 static_cast<u32>(cc)); 117 static_cast<u32>(cc));
118 118
119 // The SYNC opcode jumps to the address previously set by the SSY opcode 119 // The SYNC opcode jumps to the address previously set by the SSY opcode
120 bb.push_back(Operation(OperationCode::Sync)); 120 bb.push_back(Operation(OperationCode::PopFlowStack));
121 break; 121 break;
122 } 122 }
123 case OpCode::Id::BRK: { 123 case OpCode::Id::BRK: {
@@ -126,7 +126,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
126 static_cast<u32>(cc)); 126 static_cast<u32>(cc));
127 127
128 // The BRK opcode jumps to the address previously set by the PBK opcode 128 // The BRK opcode jumps to the address previously set by the PBK opcode
129 bb.push_back(Operation(OperationCode::Brk)); 129 bb.push_back(Operation(OperationCode::PopFlowStack));
130 break; 130 break;
131 } 131 }
132 case OpCode::Id::IPA: { 132 case OpCode::Id::IPA: {
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h
index 75d13fa4d..b8bec0d9e 100644
--- a/src/video_core/shader/shader_ir.h
+++ b/src/video_core/shader/shader_ir.h
@@ -163,13 +163,11 @@ enum class OperationCode {
163 F4TextureQueryLod, /// (MetaTexture, float[N] coords) -> float4 163 F4TextureQueryLod, /// (MetaTexture, float[N] coords) -> float4
164 F4TexelFetch, /// (MetaTexture, int[N], int) -> float4 164 F4TexelFetch, /// (MetaTexture, int[N], int) -> float4
165 165
166 Bra, /// (uint branch_target) -> void 166 Branch, /// (uint branch_target) -> void
167 Ssy, /// (uint branch_target) -> void 167 PushFlowStack, /// (uint branch_target) -> void
168 Pbk, /// (uint branch_target) -> void 168 PopFlowStack, /// () -> void
169 Sync, /// () -> void 169 Exit, /// () -> void
170 Brk, /// () -> void 170 Discard, /// () -> void
171 Exit, /// () -> void
172 Kil, /// () -> void
173 171
174 EmitVertex, /// () -> void 172 EmitVertex, /// () -> void
175 EndPrimitive, /// () -> void 173 EndPrimitive, /// () -> void