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| author | 2018-12-21 00:08:21 -0300 | |
|---|---|---|
| committer | 2019-01-15 17:54:50 -0300 | |
| commit | 4f95dc950ee483ac9d19fb98209abeb26556e26f (patch) | |
| tree | f957b50177629f776f66bf9a333acce5ab192185 /src | |
| parent | shader_decode: Implement EXIT (diff) | |
| download | yuzu-4f95dc950ee483ac9d19fb98209abeb26556e26f.tar.gz yuzu-4f95dc950ee483ac9d19fb98209abeb26556e26f.tar.xz yuzu-4f95dc950ee483ac9d19fb98209abeb26556e26f.zip | |
shader_decode: Implement IPA
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/shader/decode/other.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 2a5b70b8b..ffdc77d90 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp | |||
| @@ -45,6 +45,18 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { | |||
| 45 | } | 45 | } |
| 46 | break; | 46 | break; |
| 47 | } | 47 | } |
| 48 | case OpCode::Id::IPA: { | ||
| 49 | const auto& attribute = instr.attribute.fmt28; | ||
| 50 | const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(), | ||
| 51 | instr.ipa.sample_mode.Value()}; | ||
| 52 | |||
| 53 | const Node input_attr = GetInputAttribute(attribute.index, attribute.element, input_mode); | ||
| 54 | const Node ipa = Operation(OperationCode::Ipa, input_attr); | ||
| 55 | const Node value = GetSaturatedFloat(ipa, instr.ipa.saturate); | ||
| 56 | |||
| 57 | SetRegister(bb, instr.gpr0, value); | ||
| 58 | break; | ||
| 59 | } | ||
| 48 | default: | 60 | default: |
| 49 | UNIMPLEMENTED_MSG("Unhandled instruction: {}", opcode->get().GetName()); | 61 | UNIMPLEMENTED_MSG("Unhandled instruction: {}", opcode->get().GetName()); |
| 50 | } | 62 | } |