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| author | 2018-12-20 23:55:19 -0300 | |
|---|---|---|
| committer | 2019-01-15 17:54:50 -0300 | |
| commit | 4ccaa1402d376af14d8527c0a0bcc77be007bd3c (patch) | |
| tree | e7e91a50052583966f7963d4a440dd56b2ddb2d6 /src | |
| parent | shader_decode: Implement FMUL_C, FMUL_R and FMUL_IMM (diff) | |
| download | yuzu-4ccaa1402d376af14d8527c0a0bcc77be007bd3c.tar.gz yuzu-4ccaa1402d376af14d8527c0a0bcc77be007bd3c.tar.xz yuzu-4ccaa1402d376af14d8527c0a0bcc77be007bd3c.zip | |
shader_decode: Implement FADD_C, FADD_R and FADD_IMM
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/shader/decode/arithmetic.cpp | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic.cpp b/src/video_core/shader/decode/arithmetic.cpp index 78bca79e3..d196d94b5 100644 --- a/src/video_core/shader/decode/arithmetic.cpp +++ b/src/video_core/shader/decode/arithmetic.cpp | |||
| @@ -78,6 +78,21 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) { | |||
| 78 | SetRegister(bb, instr.gpr0, value); | 78 | SetRegister(bb, instr.gpr0, value); |
| 79 | break; | 79 | break; |
| 80 | } | 80 | } |
| 81 | case OpCode::Id::FADD_C: | ||
| 82 | case OpCode::Id::FADD_R: | ||
| 83 | case OpCode::Id::FADD_IMM: { | ||
| 84 | UNIMPLEMENTED_IF_MSG(instr.generates_cc, | ||
| 85 | "Condition codes generation in FADD is not implemented"); | ||
| 86 | |||
| 87 | op_a = GetOperandAbsNegFloat(op_a, instr.alu.abs_a, instr.alu.negate_a); | ||
| 88 | op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b); | ||
| 89 | |||
| 90 | Node value = Operation(OperationCode::FAdd, PRECISE, op_a, op_b); | ||
| 91 | value = GetSaturatedFloat(value, instr.alu.saturate_d); | ||
| 92 | |||
| 93 | SetRegister(bb, instr.gpr0, value); | ||
| 94 | break; | ||
| 95 | } | ||
| 81 | default: | 96 | default: |
| 82 | UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName()); | 97 | UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName()); |
| 83 | } | 98 | } |