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| author | 2018-12-20 23:53:50 -0300 | |
|---|---|---|
| committer | 2019-01-15 17:54:50 -0300 | |
| commit | 4c70d5b8eb68a61f5504a05dd597ecb2b04441b5 (patch) | |
| tree | d3c102f2bf3a74819aff17c13956175db38ebaaf /src | |
| parent | video_core: Replace gl_shader_decompiler (diff) | |
| download | yuzu-4c70d5b8eb68a61f5504a05dd597ecb2b04441b5.tar.gz yuzu-4c70d5b8eb68a61f5504a05dd597ecb2b04441b5.tar.xz yuzu-4c70d5b8eb68a61f5504a05dd597ecb2b04441b5.zip | |
shader_decode: Implement MOV_C and MOV_R
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/shader/decode/arithmetic.cpp | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/src/video_core/shader/decode/arithmetic.cpp b/src/video_core/shader/decode/arithmetic.cpp index 9242a7389..c297f729e 100644 --- a/src/video_core/shader/decode/arithmetic.cpp +++ b/src/video_core/shader/decode/arithmetic.cpp | |||
| @@ -11,12 +11,34 @@ namespace VideoCommon::Shader { | |||
| 11 | 11 | ||
| 12 | using Tegra::Shader::Instruction; | 12 | using Tegra::Shader::Instruction; |
| 13 | using Tegra::Shader::OpCode; | 13 | using Tegra::Shader::OpCode; |
| 14 | using Tegra::Shader::SubOp; | ||
| 14 | 15 | ||
| 15 | u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) { | 16 | u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) { |
| 16 | const Instruction instr = {program_code[pc]}; | 17 | const Instruction instr = {program_code[pc]}; |
| 17 | const auto opcode = OpCode::Decode(instr); | 18 | const auto opcode = OpCode::Decode(instr); |
| 18 | 19 | ||
| 19 | UNIMPLEMENTED(); | 20 | Node op_a = GetRegister(instr.gpr8); |
| 21 | |||
| 22 | Node op_b = [&]() -> Node { | ||
| 23 | if (instr.is_b_imm) { | ||
| 24 | return GetImmediate19(instr); | ||
| 25 | } else if (instr.is_b_gpr) { | ||
| 26 | return GetRegister(instr.gpr20); | ||
| 27 | } else { | ||
| 28 | return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset); | ||
| 29 | } | ||
| 30 | }(); | ||
| 31 | |||
| 32 | switch (opcode->get().GetId()) { | ||
| 33 | case OpCode::Id::MOV_C: | ||
| 34 | case OpCode::Id::MOV_R: { | ||
| 35 | // MOV does not have neither 'abs' nor 'neg' bits. | ||
| 36 | SetRegister(bb, instr.gpr0, op_b); | ||
| 37 | break; | ||
| 38 | } | ||
| 39 | default: | ||
| 40 | UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName()); | ||
| 41 | } | ||
| 20 | 42 | ||
| 21 | return pc; | 43 | return pc; |
| 22 | } | 44 | } |