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authorGravatar bunnei2014-12-28 16:57:16 -0500
committerGravatar bunnei2014-12-28 16:57:16 -0500
commit4bf803579f52633e7e9f02c0fc99116f89331b8d (patch)
tree2899322174893d32cb41b510d1d6453a7e8d80e4 /src
parentMerge pull request #356 from lioncash/dynusad (diff)
parentdyncom: Implement PKHBT and PKHTB. (diff)
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Merge pull request #357 from bunnei/dyncom-pkhbt-pkhtb
Implement PKHBT and PKHTB on dyncom, fix on armemu
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp59
-rw-r--r--src/core/arm/interpreter/armemu.cpp18
2 files changed, 62 insertions, 15 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 98d825272..4cd8fe6ac 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -1427,6 +1427,13 @@ typedef struct _blx_1_thumb {
1427 unsigned int instr; 1427 unsigned int instr;
1428}blx_1_thumb; 1428}blx_1_thumb;
1429 1429
1430typedef struct _pkh_inst {
1431 u32 Rm;
1432 u32 Rn;
1433 u32 Rd;
1434 u8 imm;
1435} pkh_inst;
1436
1430typedef arm_inst * ARM_INST_PTR; 1437typedef arm_inst * ARM_INST_PTR;
1431 1438
1432#define CACHE_BUFFER_SIZE (64 * 1024 * 2000) 1439#define CACHE_BUFFER_SIZE (64 * 1024 * 2000)
@@ -2376,8 +2383,30 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index)
2376 } 2383 }
2377 return inst_base; 2384 return inst_base;
2378} 2385}
2379ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("PKHBT"); } 2386
2380ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("PKHTB"); } 2387ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index)
2388{
2389 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst));
2390 pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
2391
2392 inst_base->cond = BITS(inst, 28, 31);
2393 inst_base->idx = index;
2394 inst_base->br = NON_BRANCH;
2395 inst_base->load_r15 = 0;
2396
2397 inst_cream->Rd = BITS(inst, 12, 15);
2398 inst_cream->Rn = BITS(inst, 16, 19);
2399 inst_cream->Rm = BITS(inst, 0, 3);
2400 inst_cream->imm = BITS(inst, 7, 11);
2401
2402 return inst_base;
2403}
2404
2405ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index)
2406{
2407 return INTERPRETER_TRANSLATE(pkhbt)(inst, index);
2408}
2409
2381ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index) 2410ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index)
2382{ 2411{
2383 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pld_inst)); 2412 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pld_inst));
@@ -5659,8 +5688,34 @@ unsigned InterpreterMainLoop(ARMul_State* state)
5659 FETCH_INST; 5688 FETCH_INST;
5660 GOTO_NEXT_INST; 5689 GOTO_NEXT_INST;
5661 } 5690 }
5691
5662 PKHBT_INST: 5692 PKHBT_INST:
5693 {
5694 INC_ICOUNTER;
5695 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
5696 pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
5697 RD = (RN & 0xFFFF) | ((RM << inst_cream->imm) & 0xFFFF0000);
5698 }
5699 cpu->Reg[15] += GET_INST_SIZE(cpu);
5700 INC_PC(sizeof(pkh_inst));
5701 FETCH_INST;
5702 GOTO_NEXT_INST;
5703 }
5704
5663 PKHTB_INST: 5705 PKHTB_INST:
5706 {
5707 INC_ICOUNTER;
5708 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
5709 pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
5710 int shift_imm = inst_cream->imm ? inst_cream->imm : 31;
5711 RD = ((static_cast<s32>(RM) >> shift_imm) & 0xFFFF) | (RN & 0xFFFF0000);
5712 }
5713 cpu->Reg[15] += GET_INST_SIZE(cpu);
5714 INC_PC(sizeof(pkh_inst));
5715 FETCH_INST;
5716 GOTO_NEXT_INST;
5717 }
5718
5664 PLD_INST: 5719 PLD_INST:
5665 { 5720 {
5666 INC_ICOUNTER; 5721 INC_ICOUNTER;
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 2873da897..9c6602f09 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -3100,7 +3100,6 @@ mainswitch:
3100 break; 3100 break;
3101 3101
3102 case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */ 3102 case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */
3103 //ichfly PKHBT PKHTB todo check this
3104 if ((instr & 0x70) == 0x10) { //pkhbt 3103 if ((instr & 0x70) == 0x10) { //pkhbt
3105 u8 idest = BITS(12, 15); 3104 u8 idest = BITS(12, 15);
3106 u8 rfis = BITS(16, 19); 3105 u8 rfis = BITS(16, 19);
@@ -3109,18 +3108,11 @@ mainswitch:
3109 state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000); 3108 state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000);
3110 break; 3109 break;
3111 } else if ((instr & 0x70) == 0x50) { //pkhtb 3110 } else if ((instr & 0x70) == 0x50) { //pkhtb
3112 const u8 rd_idx = BITS(12, 15); 3111 u8 rd_idx = BITS(12, 15);
3113 const u8 rn_idx = BITS(16, 19); 3112 u8 rn_idx = BITS(16, 19);
3114 const u8 rm_idx = BITS(0, 3); 3113 u8 rm_idx = BITS(0, 3);
3115 const u8 imm5 = BITS(7, 11); 3114 u8 imm5 = BITS(7, 11) ? BITS(7, 11) : 31;
3116 3115 state->Reg[rd_idx] = ((static_cast<s32>(state->Reg[rm_idx]) >> imm5) & 0xFFFF) | ((state->Reg[rn_idx]) & 0xFFFF0000);
3117 ARMword val;
3118 if (imm5 >= 32)
3119 val = (state->Reg[rm_idx] >> 31);
3120 else
3121 val = (state->Reg[rm_idx] >> imm5);
3122
3123 state->Reg[rd_idx] = (val & 0xFFFF) | ((state->Reg[rn_idx]) & 0xFFFF0000);
3124 break; 3116 break;
3125 } else if (BIT (4)) { 3117 } else if (BIT (4)) {
3126#ifdef MODE32 3118#ifdef MODE32