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| author |  Lioncash | 2015-02-14 22:34:01 -0500 |
|---|---|---|
| committer | Lioncash | 2015-02-15 00:35:50 -0500 |
| commit | 473afa453067fa95201a91fa1db3f4f8cf6e6fc0 (patch) | |
| tree | b1784a963ade92d8c74815de4d9066af0d491a1f /src | |
| parent | Merge pull request #529 from Subv/master (diff) | |
| download | yuzu-473afa453067fa95201a91fa1db3f4f8cf6e6fc0.tar.gz yuzu-473afa453067fa95201a91fa1db3f4f8cf6e6fc0.tar.xz yuzu-473afa453067fa95201a91fa1db3f4f8cf6e6fc0.zip | |
arm: Set the A bit on reset.
This enum value is ORed against in ARMul_Reset (and used to refer to all interrupt bits in the CPSR). So simply updating this is enough.
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/skyeye_common/armemu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/core/arm/skyeye_common/armemu.h b/src/core/arm/skyeye_common/armemu.h index 8bfd4e0f0..2a1c50779 100644 --- a/src/core/arm/skyeye_common/armemu.h +++ b/src/core/arm/skyeye_common/armemu.h | |||
| @@ -35,7 +35,7 @@ enum : u32 { | |||
| 35 | 35 | ||
| 36 | // Masks for groups of bits in the APSR. | 36 | // Masks for groups of bits in the APSR. |
| 37 | MODEBITS = 0x1F, | 37 | MODEBITS = 0x1F, |
| 38 | INTBITS = 0xC0, | 38 | INTBITS = 0x1C0, |
| 39 | }; | 39 | }; |
| 40 | 40 | ||
| 41 | // Different ways to start the next instruction. | 41 | // Different ways to start the next instruction. |