diff options
| author | 2021-04-19 16:36:17 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:28 -0400 | |
| commit | 469f8bb85750792cf35d5a5aa72fa5a73cf33c82 (patch) | |
| tree | e2ad225efe772d354c299650ac66d2bfc8b1f4da /src | |
| parent | shader: Add NVN storage buffer fallbacks (diff) | |
| download | yuzu-469f8bb85750792cf35d5a5aa72fa5a73cf33c82.tar.gz yuzu-469f8bb85750792cf35d5a5aa72fa5a73cf33c82.tar.xz yuzu-469f8bb85750792cf35d5a5aa72fa5a73cf33c82.zip | |
shader: Simplify code for local memory
Diffstat (limited to 'src')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/load_store_local_shared.cpp | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/load_store_local_shared.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/load_store_local_shared.cpp index e24b49721..20df163f2 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/load_store_local_shared.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/load_store_local_shared.cpp | |||
| @@ -34,6 +34,15 @@ IR::U32 Offset(TranslatorVisitor& v, u64 insn) { | |||
| 34 | } | 34 | } |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | std::pair<IR::U32, IR::U32> WordOffset(TranslatorVisitor& v, u64 insn) { | ||
| 38 | const IR::U32 offset{Offset(v, insn)}; | ||
| 39 | if (offset.IsImmediate()) { | ||
| 40 | return {v.ir.Imm32(offset.U32() / 4), offset}; | ||
| 41 | } else { | ||
| 42 | return {v.ir.ShiftRightArithmetic(offset, v.ir.Imm32(2)), offset}; | ||
| 43 | } | ||
| 44 | } | ||
| 45 | |||
| 37 | std::pair<int, bool> GetSize(u64 insn) { | 46 | std::pair<int, bool> GetSize(u64 insn) { |
| 38 | union { | 47 | union { |
| 39 | u64 raw; | 48 | u64 raw; |
| @@ -79,9 +88,7 @@ IR::U32 ShortOffset(IR::IREmitter& ir, const IR::U32& offset) { | |||
| 79 | } // Anonymous namespace | 88 | } // Anonymous namespace |
| 80 | 89 | ||
| 81 | void TranslatorVisitor::LDL(u64 insn) { | 90 | void TranslatorVisitor::LDL(u64 insn) { |
| 82 | const IR::U32 offset{Offset(*this, insn)}; | 91 | const auto [word_offset, offset]{WordOffset(*this, insn)}; |
| 83 | const IR::U32 word_offset{ir.ShiftRightArithmetic(offset, ir.Imm32(2))}; | ||
| 84 | |||
| 85 | const IR::Reg dest{Reg(insn)}; | 92 | const IR::Reg dest{Reg(insn)}; |
| 86 | const auto [bit_size, is_signed]{GetSize(insn)}; | 93 | const auto [bit_size, is_signed]{GetSize(insn)}; |
| 87 | switch (bit_size) { | 94 | switch (bit_size) { |
| @@ -133,9 +140,7 @@ void TranslatorVisitor::LDS(u64 insn) { | |||
| 133 | } | 140 | } |
| 134 | 141 | ||
| 135 | void TranslatorVisitor::STL(u64 insn) { | 142 | void TranslatorVisitor::STL(u64 insn) { |
| 136 | const IR::U32 offset{Offset(*this, insn)}; | 143 | const auto [word_offset, offset]{WordOffset(*this, insn)}; |
| 137 | const IR::U32 word_offset{ir.ShiftRightArithmetic(offset, ir.Imm32(2))}; | ||
| 138 | |||
| 139 | const IR::Reg reg{Reg(insn)}; | 144 | const IR::Reg reg{Reg(insn)}; |
| 140 | const IR::U32 src{X(reg)}; | 145 | const IR::U32 src{X(reg)}; |
| 141 | const int bit_size{GetSize(insn).first}; | 146 | const int bit_size{GetSize(insn).first}; |