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authorGravatar bunnei2017-10-23 00:13:12 -0400
committerGravatar bunnei2017-10-23 00:13:12 -0400
commit45db4bb3ea9e5a46db598eb99957bfd7d7a135f7 (patch)
tree638b55751be07e580ed4bc505c65ba27384e5927 /src
parentnso: Load more common submodules. (diff)
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logging: Rename category "Core_ARM11" to "Core_ARM".
Diffstat (limited to 'src')
-rw-r--r--src/common/logging/backend.cpp2
-rw-r--r--src/common/logging/log.h2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp28
-rw-r--r--src/core/arm/dyncom/arm_dyncom_trans.cpp2
-rw-r--r--src/core/arm/skyeye_common/armstate.cpp2
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.cpp12
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.h2
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpdouble.cpp76
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpsingle.cpp50
-rw-r--r--src/core/core.cpp2
10 files changed, 89 insertions, 89 deletions
diff --git a/src/common/logging/backend.cpp b/src/common/logging/backend.cpp
index dc10a7bc6..13f915a01 100644
--- a/src/common/logging/backend.cpp
+++ b/src/common/logging/backend.cpp
@@ -21,7 +21,7 @@ namespace Log {
21 SUB(Common, Filesystem) \ 21 SUB(Common, Filesystem) \
22 SUB(Common, Memory) \ 22 SUB(Common, Memory) \
23 CLS(Core) \ 23 CLS(Core) \
24 SUB(Core, ARM11) \ 24 SUB(Core, ARM) \
25 SUB(Core, Timing) \ 25 SUB(Core, Timing) \
26 CLS(Config) \ 26 CLS(Config) \
27 CLS(Debug) \ 27 CLS(Debug) \
diff --git a/src/common/logging/log.h b/src/common/logging/log.h
index 8e4601d6c..35b5af3cb 100644
--- a/src/common/logging/log.h
+++ b/src/common/logging/log.h
@@ -37,7 +37,7 @@ enum class Class : ClassType {
37 Common_Filesystem, ///< Filesystem interface library 37 Common_Filesystem, ///< Filesystem interface library
38 Common_Memory, ///< Memory mapping and management functions 38 Common_Memory, ///< Memory mapping and management functions
39 Core, ///< LLE emulation core 39 Core, ///< LLE emulation core
40 Core_ARM11, ///< ARM11 CPU core 40 Core_ARM, ///< ARM CPU core
41 Core_Timing, ///< CoreTiming functions 41 Core_Timing, ///< CoreTiming functions
42 Config, ///< Emulator configuration (including commandline) 42 Config, ///< Emulator configuration (including commandline)
43 Debug, ///< Debugging tools 43 Debug, ///< Debugging tools
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 3522d1e82..fc2d6aabc 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -230,7 +230,7 @@ static unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sh
230} 230}
231 231
232#define DEBUG_MSG \ 232#define DEBUG_MSG \
233 LOG_DEBUG(Core_ARM11, "inst is %x", inst); \ 233 LOG_DEBUG(Core_ARM, "inst is %x", inst); \
234 CITRA_IGNORE_EXIT(0) 234 CITRA_IGNORE_EXIT(0)
235 235
236#define LnSWoUB(s) glue(LnSWoUB, s) 236#define LnSWoUB(s) glue(LnSWoUB, s)
@@ -769,7 +769,7 @@ static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_ins
769 inst_index = table_length - 4; 769 inst_index = table_length - 4;
770 *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index); 770 *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
771 } else { 771 } else {
772 LOG_ERROR(Core_ARM11, "thumb decoder error"); 772 LOG_ERROR(Core_ARM, "thumb decoder error");
773 } 773 }
774 break; 774 break;
775 case 28: 775 case 28:
@@ -827,9 +827,9 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
827 827
828 int idx; 828 int idx;
829 if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) { 829 if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
830 LOG_ERROR(Core_ARM11, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32, 830 LOG_ERROR(Core_ARM, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32,
831 phys_addr, inst); 831 phys_addr, inst);
832 LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr, 832 LOG_ERROR(Core_ARM, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
833 cpu->TFlag, cpu->Reg[15]); 833 cpu->TFlag, cpu->Reg[15]);
834 CITRA_IGNORE_EXIT(-1); 834 CITRA_IGNORE_EXIT(-1);
835 } 835 }
@@ -1802,7 +1802,7 @@ BIC_INST : {
1802BKPT_INST : { 1802BKPT_INST : {
1803 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 1803 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1804 bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component; 1804 bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
1805 LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm); 1805 LOG_DEBUG(Core_ARM, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
1806 } 1806 }
1807 cpu->Reg[15] += cpu->GetInstructionSize(); 1807 cpu->Reg[15] += cpu->GetInstructionSize();
1808 INC_PC(sizeof(bkpt_inst)); 1808 INC_PC(sizeof(bkpt_inst));
@@ -2017,7 +2017,7 @@ EOR_INST : {
2017} 2017}
2018LDC_INST : { 2018LDC_INST : {
2019 // Instruction not implemented 2019 // Instruction not implemented
2020 // LOG_CRITICAL(Core_ARM11, "unimplemented instruction"); 2020 // LOG_CRITICAL(Core_ARM, "unimplemented instruction");
2021 cpu->Reg[15] += cpu->GetInstructionSize(); 2021 cpu->Reg[15] += cpu->GetInstructionSize();
2022 INC_PC(sizeof(ldc_inst)); 2022 INC_PC(sizeof(ldc_inst));
2023 FETCH_INST; 2023 FETCH_INST;
@@ -2368,7 +2368,7 @@ MCRR_INST : {
2368 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2368 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2369 mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component; 2369 mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
2370 2370
2371 LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u", 2371 LOG_ERROR(Core_ARM, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
2372 inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, 2372 inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
2373 inst_cream->rt2); 2373 inst_cream->rt2);
2374 } 2374 }
@@ -2451,7 +2451,7 @@ MRRC_INST : {
2451 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2451 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2452 mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component; 2452 mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
2453 2453
2454 LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u", 2454 LOG_ERROR(Core_ARM, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
2455 inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, 2455 inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
2456 inst_cream->rt2); 2456 inst_cream->rt2);
2457 } 2457 }
@@ -3078,7 +3078,7 @@ SETEND_INST : {
3078 else 3078 else
3079 cpu->Cpsr &= ~(1 << 9); 3079 cpu->Cpsr &= ~(1 << 9);
3080 3080
3081 LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE"); 3081 LOG_WARNING(Core_ARM, "SETEND %s executed", big_endian ? "BE" : "LE");
3082 3082
3083 cpu->Reg[15] += cpu->GetInstructionSize(); 3083 cpu->Reg[15] += cpu->GetInstructionSize();
3084 INC_PC(sizeof(setend_inst)); 3084 INC_PC(sizeof(setend_inst));
@@ -3089,7 +3089,7 @@ SETEND_INST : {
3089SEV_INST : { 3089SEV_INST : {
3090 // Stubbed, as SEV is a hint instruction. 3090 // Stubbed, as SEV is a hint instruction.
3091 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3091 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3092 LOG_TRACE(Core_ARM11, "SEV executed."); 3092 LOG_TRACE(Core_ARM, "SEV executed.");
3093 } 3093 }
3094 3094
3095 cpu->Reg[15] += cpu->GetInstructionSize(); 3095 cpu->Reg[15] += cpu->GetInstructionSize();
@@ -3539,7 +3539,7 @@ SSAT16_INST : {
3539 3539
3540STC_INST : { 3540STC_INST : {
3541 // Instruction not implemented 3541 // Instruction not implemented
3542 // LOG_CRITICAL(Core_ARM11, "unimplemented instruction"); 3542 // LOG_CRITICAL(Core_ARM, "unimplemented instruction");
3543 cpu->Reg[15] += cpu->GetInstructionSize(); 3543 cpu->Reg[15] += cpu->GetInstructionSize();
3544 INC_PC(sizeof(stc_inst)); 3544 INC_PC(sizeof(stc_inst));
3545 FETCH_INST; 3545 FETCH_INST;
@@ -4529,7 +4529,7 @@ UXTB16_INST : {
4529WFE_INST : { 4529WFE_INST : {
4530 // Stubbed, as WFE is a hint instruction. 4530 // Stubbed, as WFE is a hint instruction.
4531 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4531 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4532 LOG_TRACE(Core_ARM11, "WFE executed."); 4532 LOG_TRACE(Core_ARM, "WFE executed.");
4533 } 4533 }
4534 4534
4535 cpu->Reg[15] += cpu->GetInstructionSize(); 4535 cpu->Reg[15] += cpu->GetInstructionSize();
@@ -4541,7 +4541,7 @@ WFE_INST : {
4541WFI_INST : { 4541WFI_INST : {
4542 // Stubbed, as WFI is a hint instruction. 4542 // Stubbed, as WFI is a hint instruction.
4543 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4543 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4544 LOG_TRACE(Core_ARM11, "WFI executed."); 4544 LOG_TRACE(Core_ARM, "WFI executed.");
4545 } 4545 }
4546 4546
4547 cpu->Reg[15] += cpu->GetInstructionSize(); 4547 cpu->Reg[15] += cpu->GetInstructionSize();
@@ -4553,7 +4553,7 @@ WFI_INST : {
4553YIELD_INST : { 4553YIELD_INST : {
4554 // Stubbed, as YIELD is a hint instruction. 4554 // Stubbed, as YIELD is a hint instruction.
4555 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4555 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4556 LOG_TRACE(Core_ARM11, "YIELD executed."); 4556 LOG_TRACE(Core_ARM, "YIELD executed.");
4557 } 4557 }
4558 4558
4559 cpu->Reg[15] += cpu->GetInstructionSize(); 4559 cpu->Reg[15] += cpu->GetInstructionSize();
diff --git a/src/core/arm/dyncom/arm_dyncom_trans.cpp b/src/core/arm/dyncom/arm_dyncom_trans.cpp
index 780638638..9cd6c0dea 100644
--- a/src/core/arm/dyncom/arm_dyncom_trans.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_trans.cpp
@@ -185,7 +185,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index) {
185 inst_cream->opcode_1 = BITS(inst, 20, 23); 185 inst_cream->opcode_1 = BITS(inst, 20, 23);
186 inst_cream->inst = inst; 186 inst_cream->inst = inst;
187 187
188 LOG_TRACE(Core_ARM11, "inst %x index %x", inst, index); 188 LOG_TRACE(Core_ARM, "inst %x index %x", inst, index);
189 return inst_base; 189 return inst_base;
190} 190}
191static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) { 191static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) {
diff --git a/src/core/arm/skyeye_common/armstate.cpp b/src/core/arm/skyeye_common/armstate.cpp
index c36b0208f..92b644825 100644
--- a/src/core/arm/skyeye_common/armstate.cpp
+++ b/src/core/arm/skyeye_common/armstate.cpp
@@ -428,7 +428,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
428 } 428 }
429 } 429 }
430 430
431 LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", 431 LOG_ERROR(Core_ARM, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.",
432 crn, crm, opcode_1, opcode_2); 432 crn, crm, opcode_1, opcode_2);
433 return 0; 433 return 0;
434} 434}
diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp
index f36c75a07..0466b999a 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfp.cpp
@@ -90,23 +90,23 @@ void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m) {
90 90
91/* Miscellaneous functions */ 91/* Miscellaneous functions */
92s32 vfp_get_float(ARMul_State* state, unsigned int reg) { 92s32 vfp_get_float(ARMul_State* state, unsigned int reg) {
93 LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]", reg, state->ExtReg[reg]); 93 LOG_TRACE(Core_ARM, "VFP get float: s%d=[%08x]", reg, state->ExtReg[reg]);
94 return state->ExtReg[reg]; 94 return state->ExtReg[reg];
95} 95}
96 96
97void vfp_put_float(ARMul_State* state, s32 val, unsigned int reg) { 97void vfp_put_float(ARMul_State* state, s32 val, unsigned int reg) {
98 LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]", reg, val); 98 LOG_TRACE(Core_ARM, "VFP put float: s%d <= [%08x]", reg, val);
99 state->ExtReg[reg] = val; 99 state->ExtReg[reg] = val;
100} 100}
101 101
102u64 vfp_get_double(ARMul_State* state, unsigned int reg) { 102u64 vfp_get_double(ARMul_State* state, unsigned int reg) {
103 u64 result = ((u64)state->ExtReg[reg * 2 + 1]) << 32 | state->ExtReg[reg * 2]; 103 u64 result = ((u64)state->ExtReg[reg * 2 + 1]) << 32 | state->ExtReg[reg * 2];
104 LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]", reg * 2 + 1, reg * 2, result); 104 LOG_TRACE(Core_ARM, "VFP get double: s[%d-%d]=[%016llx]", reg * 2 + 1, reg * 2, result);
105 return result; 105 return result;
106} 106}
107 107
108void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg) { 108void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg) {
109 LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]", reg * 2 + 1, reg * 2, 109 LOG_TRACE(Core_ARM, "VFP put double: s[%d-%d] <= [%08x-%08x]", reg * 2 + 1, reg * 2,
110 (u32)(val >> 32), (u32)(val & 0xffffffff)); 110 (u32)(val >> 32), (u32)(val & 0xffffffff));
111 state->ExtReg[reg * 2] = (u32)(val & 0xffffffff); 111 state->ExtReg[reg * 2] = (u32)(val & 0xffffffff);
112 state->ExtReg[reg * 2 + 1] = (u32)(val >> 32); 112 state->ExtReg[reg * 2 + 1] = (u32)(val >> 32);
@@ -116,10 +116,10 @@ void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg) {
116 * Process bitmask of exception conditions. (from vfpmodule.c) 116 * Process bitmask of exception conditions. (from vfpmodule.c)
117 */ 117 */
118void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr) { 118void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr) {
119 LOG_TRACE(Core_ARM11, "VFP: raising exceptions %08x", exceptions); 119 LOG_TRACE(Core_ARM, "VFP: raising exceptions %08x", exceptions);
120 120
121 if (exceptions == VFP_EXCEPTION_ERROR) { 121 if (exceptions == VFP_EXCEPTION_ERROR) {
122 LOG_CRITICAL(Core_ARM11, "unhandled bounce %x", inst); 122 LOG_CRITICAL(Core_ARM, "unhandled bounce %x", inst);
123 Crash(); 123 Crash();
124 } 124 }
125 125
diff --git a/src/core/arm/skyeye_common/vfp/vfp.h b/src/core/arm/skyeye_common/vfp/vfp.h
index 60a63e6de..fe9c4dac8 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.h
+++ b/src/core/arm/skyeye_common/vfp/vfp.h
@@ -22,7 +22,7 @@
22 22
23#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */ 23#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
24 24
25#define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM11, "in func %s, " #x " untested", __FUNCTION__); 25#define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM, "in func %s, " #x " untested", __FUNCTION__);
26#define CHECK_VFP_ENABLED 26#define CHECK_VFP_ENABLED
27#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_FPSCR]); 27#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
28 28
diff --git a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
index 735cf1a09..e5cb54aab 100644
--- a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
@@ -62,7 +62,7 @@ static struct vfp_double vfp_double_default_qnan = {
62}; 62};
63 63
64static void vfp_double_dump(const char* str, struct vfp_double* d) { 64static void vfp_double_dump(const char* str, struct vfp_double* d) {
65 LOG_TRACE(Core_ARM11, "VFP: %s: sign=%d exponent=%d significand=%016llx", str, d->sign != 0, 65 LOG_TRACE(Core_ARM, "VFP: %s: sign=%d exponent=%d significand=%016llx", str, d->sign != 0,
66 d->exponent, d->significand); 66 d->exponent, d->significand);
67} 67}
68 68
@@ -164,7 +164,7 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double* vd,
164 } else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0)) 164 } else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0))
165 incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1; 165 incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1;
166 166
167 LOG_TRACE(Core_ARM11, "VFP: rounding increment = 0x%08llx", incr); 167 LOG_TRACE(Core_ARM, "VFP: rounding increment = 0x%08llx", incr);
168 168
169 /* 169 /*
170 * Is our rounding going to overflow? 170 * Is our rounding going to overflow?
@@ -219,7 +219,7 @@ pack:
219 vfp_double_dump("pack: final", vd); 219 vfp_double_dump("pack: final", vd);
220 { 220 {
221 s64 d = vfp_double_pack(vd); 221 s64 d = vfp_double_pack(vd);
222 LOG_TRACE(Core_ARM11, "VFP: %s: d(d%d)=%016llx exceptions=%08x", func, dd, d, exceptions); 222 LOG_TRACE(Core_ARM, "VFP: %s: d(d%d)=%016llx exceptions=%08x", func, dd, d, exceptions);
223 vfp_put_double(state, d, dd); 223 vfp_put_double(state, d, dd);
224 } 224 }
225 return exceptions; 225 return exceptions;
@@ -272,25 +272,25 @@ static u32 vfp_propagate_nan(struct vfp_double* vdd, struct vfp_double* vdn, str
272 * Extended operations 272 * Extended operations
273 */ 273 */
274static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { 274static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
275 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 275 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
276 vfp_put_double(state, vfp_double_packed_abs(vfp_get_double(state, dm)), dd); 276 vfp_put_double(state, vfp_double_packed_abs(vfp_get_double(state, dm)), dd);
277 return 0; 277 return 0;
278} 278}
279 279
280static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { 280static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
281 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 281 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
282 vfp_put_double(state, vfp_get_double(state, dm), dd); 282 vfp_put_double(state, vfp_get_double(state, dm), dd);
283 return 0; 283 return 0;
284} 284}
285 285
286static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { 286static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
287 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 287 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
288 vfp_put_double(state, vfp_double_packed_negate(vfp_get_double(state, dm)), dd); 288 vfp_put_double(state, vfp_double_packed_negate(vfp_get_double(state, dm)), dd);
289 return 0; 289 return 0;
290} 290}
291 291
292static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { 292static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
293 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 293 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
294 vfp_double vdm, vdd, *vdp; 294 vfp_double vdm, vdd, *vdp;
295 int ret, tm; 295 int ret, tm;
296 u32 exceptions = 0; 296 u32 exceptions = 0;
@@ -387,7 +387,7 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
387 s64 d, m; 387 s64 d, m;
388 u32 ret = 0; 388 u32 ret = 0;
389 389
390 LOG_TRACE(Core_ARM11, "In %s, state=0x%p, fpscr=0x%x", __FUNCTION__, state, fpscr); 390 LOG_TRACE(Core_ARM, "In %s, state=0x%p, fpscr=0x%x", __FUNCTION__, state, fpscr);
391 m = vfp_get_double(state, dm); 391 m = vfp_get_double(state, dm);
392 if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) { 392 if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) {
393 ret |= FPSCR_CFLAG | FPSCR_VFLAG; 393 ret |= FPSCR_CFLAG | FPSCR_VFLAG;
@@ -444,28 +444,28 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
444 ret |= FPSCR_CFLAG; 444 ret |= FPSCR_CFLAG;
445 } 445 }
446 } 446 }
447 LOG_TRACE(Core_ARM11, "In %s, state=0x%p, ret=0x%x", __FUNCTION__, state, ret); 447 LOG_TRACE(Core_ARM, "In %s, state=0x%p, ret=0x%x", __FUNCTION__, state, ret);
448 448
449 return ret; 449 return ret;
450} 450}
451 451
452static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { 452static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
453 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 453 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
454 return vfp_compare(state, dd, 0, dm, fpscr); 454 return vfp_compare(state, dd, 0, dm, fpscr);
455} 455}
456 456
457static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { 457static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
458 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 458 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
459 return vfp_compare(state, dd, 1, dm, fpscr); 459 return vfp_compare(state, dd, 1, dm, fpscr);
460} 460}
461 461
462static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { 462static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
463 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 463 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
464 return vfp_compare(state, dd, 0, VFP_REG_ZERO, fpscr); 464 return vfp_compare(state, dd, 0, VFP_REG_ZERO, fpscr);
465} 465}
466 466
467static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { 467static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
468 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 468 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
469 return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr); 469 return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr);
470} 470}
471 471
@@ -475,7 +475,7 @@ static u32 vfp_double_fcvts(ARMul_State* state, int sd, int unused, int dm, u32
475 int tm; 475 int tm;
476 u32 exceptions = 0; 476 u32 exceptions = 0;
477 477
478 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 478 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
479 exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr); 479 exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr);
480 480
481 tm = vfp_double_type(&vdm); 481 tm = vfp_double_type(&vdm);
@@ -516,7 +516,7 @@ static u32 vfp_double_fuito(ARMul_State* state, int dd, int unused, int dm, u32
516 struct vfp_double vdm; 516 struct vfp_double vdm;
517 u32 m = vfp_get_float(state, dm); 517 u32 m = vfp_get_float(state, dm);
518 518
519 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 519 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
520 vdm.sign = 0; 520 vdm.sign = 0;
521 vdm.exponent = 1023 + 63 - 1; 521 vdm.exponent = 1023 + 63 - 1;
522 vdm.significand = (u64)m; 522 vdm.significand = (u64)m;
@@ -528,7 +528,7 @@ static u32 vfp_double_fsito(ARMul_State* state, int dd, int unused, int dm, u32
528 struct vfp_double vdm; 528 struct vfp_double vdm;
529 u32 m = vfp_get_float(state, dm); 529 u32 m = vfp_get_float(state, dm);
530 530
531 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 531 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
532 vdm.sign = (m & 0x80000000) >> 16; 532 vdm.sign = (m & 0x80000000) >> 16;
533 vdm.exponent = 1023 + 63 - 1; 533 vdm.exponent = 1023 + 63 - 1;
534 vdm.significand = vdm.sign ? (~m + 1) : m; 534 vdm.significand = vdm.sign ? (~m + 1) : m;
@@ -542,7 +542,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
542 int rmode = fpscr & FPSCR_RMODE_MASK; 542 int rmode = fpscr & FPSCR_RMODE_MASK;
543 int tm; 543 int tm;
544 544
545 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 545 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
546 exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr); 546 exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr);
547 547
548 /* 548 /*
@@ -611,7 +611,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
611 } 611 }
612 } 612 }
613 613
614 LOG_TRACE(Core_ARM11, "VFP: ftoui: d(s%d)=%08x exceptions=%08x", sd, d, exceptions); 614 LOG_TRACE(Core_ARM, "VFP: ftoui: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
615 615
616 vfp_put_float(state, d, sd); 616 vfp_put_float(state, d, sd);
617 617
@@ -619,7 +619,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
619} 619}
620 620
621static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) { 621static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) {
622 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 622 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
623 return vfp_double_ftoui(state, sd, unused, dm, 623 return vfp_double_ftoui(state, sd, unused, dm,
624 (fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO); 624 (fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO);
625} 625}
@@ -630,7 +630,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
630 int rmode = fpscr & FPSCR_RMODE_MASK; 630 int rmode = fpscr & FPSCR_RMODE_MASK;
631 int tm; 631 int tm;
632 632
633 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 633 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
634 exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr); 634 exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr);
635 vfp_double_dump("VDM", &vdm); 635 vfp_double_dump("VDM", &vdm);
636 636
@@ -694,7 +694,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
694 } 694 }
695 } 695 }
696 696
697 LOG_TRACE(Core_ARM11, "VFP: ftosi: d(s%d)=%08x exceptions=%08x", sd, d, exceptions); 697 LOG_TRACE(Core_ARM, "VFP: ftosi: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
698 698
699 vfp_put_float(state, (s32)d, sd); 699 vfp_put_float(state, (s32)d, sd);
700 700
@@ -702,7 +702,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
702} 702}
703 703
704static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { 704static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
705 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 705 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
706 return vfp_double_ftosi(state, dd, unused, dm, 706 return vfp_double_ftosi(state, dd, unused, dm,
707 (fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO); 707 (fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO);
708} 708}
@@ -784,7 +784,7 @@ u32 vfp_double_add(struct vfp_double* vdd, struct vfp_double* vdn, struct vfp_do
784 u64 m_sig; 784 u64 m_sig;
785 785
786 if (vdn->significand & (1ULL << 63) || vdm->significand & (1ULL << 63)) { 786 if (vdn->significand & (1ULL << 63) || vdm->significand & (1ULL << 63)) {
787 LOG_INFO(Core_ARM11, "VFP: bad FP values in %s", __func__); 787 LOG_INFO(Core_ARM, "VFP: bad FP values in %s", __func__);
788 vfp_double_dump("VDN", vdn); 788 vfp_double_dump("VDN", vdn);
789 vfp_double_dump("VDM", vdm); 789 vfp_double_dump("VDM", vdm);
790 } 790 }
@@ -849,7 +849,7 @@ u32 vfp_double_multiply(struct vfp_double* vdd, struct vfp_double* vdn, struct v
849 */ 849 */
850 if (vdn->exponent < vdm->exponent) { 850 if (vdn->exponent < vdm->exponent) {
851 std::swap(vdm, vdn); 851 std::swap(vdm, vdn);
852 LOG_TRACE(Core_ARM11, "VFP: swapping M <-> N"); 852 LOG_TRACE(Core_ARM, "VFP: swapping M <-> N");
853 } 853 }
854 854
855 vdd->sign = vdn->sign ^ vdm->sign; 855 vdd->sign = vdn->sign ^ vdm->sign;
@@ -931,7 +931,7 @@ static u32 vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, in
931 * sd = sd + (sn * sm) 931 * sd = sd + (sn * sm)
932 */ 932 */
933static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { 933static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) {
934 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 934 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
935 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, 0, "fmac"); 935 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, 0, "fmac");
936} 936}
937 937
@@ -939,7 +939,7 @@ static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
939 * sd = sd - (sn * sm) 939 * sd = sd - (sn * sm)
940 */ 940 */
941static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { 941static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) {
942 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 942 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
943 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_MULTIPLY, "fnmac"); 943 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_MULTIPLY, "fnmac");
944} 944}
945 945
@@ -947,7 +947,7 @@ static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
947 * sd = -sd + (sn * sm) 947 * sd = -sd + (sn * sm)
948 */ 948 */
949static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { 949static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) {
950 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 950 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
951 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT, "fmsc"); 951 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT, "fmsc");
952} 952}
953 953
@@ -955,7 +955,7 @@ static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
955 * sd = -sd - (sn * sm) 955 * sd = -sd - (sn * sm)
956 */ 956 */
957static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { 957static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) {
958 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 958 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
959 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, 959 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY,
960 "fnmsc"); 960 "fnmsc");
961} 961}
@@ -967,7 +967,7 @@ static u32 vfp_double_fmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
967 struct vfp_double vdd, vdn, vdm; 967 struct vfp_double vdd, vdn, vdm;
968 u32 exceptions = 0; 968 u32 exceptions = 0;
969 969
970 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 970 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
971 exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr); 971 exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr);
972 if (vdn.exponent == 0 && vdn.significand) 972 if (vdn.exponent == 0 && vdn.significand)
973 vfp_double_normalise_denormal(&vdn); 973 vfp_double_normalise_denormal(&vdn);
@@ -987,7 +987,7 @@ static u32 vfp_double_fnmul(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
987 struct vfp_double vdd, vdn, vdm; 987 struct vfp_double vdd, vdn, vdm;
988 u32 exceptions = 0; 988 u32 exceptions = 0;
989 989
990 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 990 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
991 exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr); 991 exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr);
992 if (vdn.exponent == 0 && vdn.significand) 992 if (vdn.exponent == 0 && vdn.significand)
993 vfp_double_normalise_denormal(&vdn); 993 vfp_double_normalise_denormal(&vdn);
@@ -1009,7 +1009,7 @@ static u32 vfp_double_fadd(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
1009 struct vfp_double vdd, vdn, vdm; 1009 struct vfp_double vdd, vdn, vdm;
1010 u32 exceptions = 0; 1010 u32 exceptions = 0;
1011 1011
1012 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 1012 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
1013 exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr); 1013 exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr);
1014 if (vdn.exponent == 0 && vdn.significand) 1014 if (vdn.exponent == 0 && vdn.significand)
1015 vfp_double_normalise_denormal(&vdn); 1015 vfp_double_normalise_denormal(&vdn);
@@ -1030,7 +1030,7 @@ static u32 vfp_double_fsub(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
1030 struct vfp_double vdd, vdn, vdm; 1030 struct vfp_double vdd, vdn, vdm;
1031 u32 exceptions = 0; 1031 u32 exceptions = 0;
1032 1032
1033 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 1033 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
1034 exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr); 1034 exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr);
1035 if (vdn.exponent == 0 && vdn.significand) 1035 if (vdn.exponent == 0 && vdn.significand)
1036 vfp_double_normalise_denormal(&vdn); 1036 vfp_double_normalise_denormal(&vdn);
@@ -1057,7 +1057,7 @@ static u32 vfp_double_fdiv(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
1057 u32 exceptions = 0; 1057 u32 exceptions = 0;
1058 int tm, tn; 1058 int tm, tn;
1059 1059
1060 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 1060 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
1061 exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr); 1061 exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr);
1062 exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr); 1062 exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr);
1063 1063
@@ -1175,7 +1175,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr) {
1175 unsigned int vecitr, veclen, vecstride; 1175 unsigned int vecitr, veclen, vecstride;
1176 struct op* fop; 1176 struct op* fop;
1177 1177
1178 LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); 1178 LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
1179 vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)); 1179 vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK));
1180 1180
1181 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)]; 1181 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
@@ -1206,7 +1206,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr) {
1206 else 1206 else
1207 veclen = fpscr & FPSCR_LENGTH_MASK; 1207 veclen = fpscr & FPSCR_LENGTH_MASK;
1208 1208
1209 LOG_TRACE(Core_ARM11, "VFP: vecstride=%u veclen=%u", vecstride, 1209 LOG_TRACE(Core_ARM, "VFP: vecstride=%u veclen=%u", vecstride,
1210 (veclen >> FPSCR_LENGTH_BIT) + 1); 1210 (veclen >> FPSCR_LENGTH_BIT) + 1);
1211 1211
1212 if (!fop->fn) { 1212 if (!fop->fn) {
@@ -1220,14 +1220,14 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr) {
1220 1220
1221 type = (fop->flags & OP_SD) ? 's' : 'd'; 1221 type = (fop->flags & OP_SD) ? 's' : 'd';
1222 if (op == FOP_EXT) 1222 if (op == FOP_EXT)
1223 LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = op[%u] (d%u)", vecitr >> FPSCR_LENGTH_BIT, 1223 LOG_TRACE(Core_ARM, "VFP: itr%d (%c%u) = op[%u] (d%u)", vecitr >> FPSCR_LENGTH_BIT,
1224 type, dest, dn, dm); 1224 type, dest, dn, dm);
1225 else 1225 else
1226 LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)", 1226 LOG_TRACE(Core_ARM, "VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)",
1227 vecitr >> FPSCR_LENGTH_BIT, type, dest, dn, FOP_TO_IDX(op), dm); 1227 vecitr >> FPSCR_LENGTH_BIT, type, dest, dn, FOP_TO_IDX(op), dm);
1228 1228
1229 except = fop->fn(state, dest, dn, dm, fpscr); 1229 except = fop->fn(state, dest, dn, dm, fpscr);
1230 LOG_TRACE(Core_ARM11, "VFP: itr%d: exceptions=%08x", vecitr >> FPSCR_LENGTH_BIT, except); 1230 LOG_TRACE(Core_ARM, "VFP: itr%d: exceptions=%08x", vecitr >> FPSCR_LENGTH_BIT, except);
1231 1231
1232 exceptions |= except & ~VFP_NAN_FLAG; 1232 exceptions |= except & ~VFP_NAN_FLAG;
1233 1233
diff --git a/src/core/arm/skyeye_common/vfp/vfpsingle.cpp b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
index 1f9142abc..108f03aa9 100644
--- a/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
@@ -65,7 +65,7 @@ static struct vfp_single vfp_single_default_qnan = {
65}; 65};
66 66
67static void vfp_single_dump(const char* str, struct vfp_single* s) { 67static void vfp_single_dump(const char* str, struct vfp_single* s) {
68 LOG_TRACE(Core_ARM11, "%s: sign=%d exponent=%d significand=%08x", str, s->sign != 0, 68 LOG_TRACE(Core_ARM, "%s: sign=%d exponent=%d significand=%08x", str, s->sign != 0,
69 s->exponent, s->significand); 69 s->exponent, s->significand);
70} 70}
71 71
@@ -167,7 +167,7 @@ u32 vfp_single_normaliseround(ARMul_State* state, int sd, struct vfp_single* vs,
167 } else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vs->sign != 0)) 167 } else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vs->sign != 0))
168 incr = (1 << (VFP_SINGLE_LOW_BITS + 1)) - 1; 168 incr = (1 << (VFP_SINGLE_LOW_BITS + 1)) - 1;
169 169
170 LOG_TRACE(Core_ARM11, "rounding increment = 0x%08x", incr); 170 LOG_TRACE(Core_ARM, "rounding increment = 0x%08x", incr);
171 171
172 /* 172 /*
173 * Is our rounding going to overflow? 173 * Is our rounding going to overflow?
@@ -222,7 +222,7 @@ pack:
222 vfp_single_dump("pack: final", vs); 222 vfp_single_dump("pack: final", vs);
223 { 223 {
224 s32 d = vfp_single_pack(vs); 224 s32 d = vfp_single_pack(vs);
225 LOG_TRACE(Core_ARM11, "%s: d(s%d)=%08x exceptions=%08x", func, sd, d, exceptions); 225 LOG_TRACE(Core_ARM, "%s: d(s%d)=%08x exceptions=%08x", func, sd, d, exceptions);
226 vfp_put_float(state, d, sd); 226 vfp_put_float(state, d, sd);
227 } 227 }
228 228
@@ -305,7 +305,7 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand) {
305 u32 z, a; 305 u32 z, a;
306 306
307 if ((significand & 0xc0000000) != 0x40000000) { 307 if ((significand & 0xc0000000) != 0x40000000) {
308 LOG_TRACE(Core_ARM11, "invalid significand"); 308 LOG_TRACE(Core_ARM, "invalid significand");
309 } 309 }
310 310
311 a = significand << 1; 311 a = significand << 1;
@@ -395,7 +395,7 @@ static u32 vfp_single_fsqrt(ARMul_State* state, int sd, int unused, s32 m, u32 f
395 term = (u64)vsd.significand * vsd.significand; 395 term = (u64)vsd.significand * vsd.significand;
396 rem = ((u64)vsm.significand << 32) - term; 396 rem = ((u64)vsm.significand << 32) - term;
397 397
398 LOG_TRACE(Core_ARM11, "term=%016" PRIx64 "rem=%016" PRIx64, term, rem); 398 LOG_TRACE(Core_ARM, "term=%016" PRIx64 "rem=%016" PRIx64, term, rem);
399 399
400 while (rem < 0) { 400 while (rem < 0) {
401 vsd.significand -= 1; 401 vsd.significand -= 1;
@@ -634,7 +634,7 @@ static u32 vfp_single_ftoui(ARMul_State* state, int sd, int unused, s32 m, u32 f
634 } 634 }
635 } 635 }
636 636
637 LOG_TRACE(Core_ARM11, "ftoui: d(s%d)=%08x exceptions=%08x", sd, d, exceptions); 637 LOG_TRACE(Core_ARM, "ftoui: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
638 638
639 vfp_put_float(state, d, sd); 639 vfp_put_float(state, d, sd);
640 640
@@ -715,7 +715,7 @@ static u32 vfp_single_ftosi(ARMul_State* state, int sd, int unused, s32 m, u32 f
715 } 715 }
716 } 716 }
717 717
718 LOG_TRACE(Core_ARM11, "ftosi: d(s%d)=%08x exceptions=%08x", sd, d, exceptions); 718 LOG_TRACE(Core_ARM, "ftosi: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
719 719
720 vfp_put_float(state, (s32)d, sd); 720 vfp_put_float(state, (s32)d, sd);
721 721
@@ -802,7 +802,7 @@ static u32 vfp_single_add(struct vfp_single* vsd, struct vfp_single* vsn, struct
802 u32 exp_diff, m_sig; 802 u32 exp_diff, m_sig;
803 803
804 if (vsn->significand & 0x80000000 || vsm->significand & 0x80000000) { 804 if (vsn->significand & 0x80000000 || vsm->significand & 0x80000000) {
805 LOG_WARNING(Core_ARM11, "bad FP values"); 805 LOG_WARNING(Core_ARM, "bad FP values");
806 vfp_single_dump("VSN", vsn); 806 vfp_single_dump("VSN", vsn);
807 vfp_single_dump("VSM", vsm); 807 vfp_single_dump("VSM", vsm);
808 } 808 }
@@ -867,7 +867,7 @@ static u32 vfp_single_multiply(struct vfp_single* vsd, struct vfp_single* vsn,
867 */ 867 */
868 if (vsn->exponent < vsm->exponent) { 868 if (vsn->exponent < vsm->exponent) {
869 std::swap(vsm, vsn); 869 std::swap(vsm, vsn);
870 LOG_TRACE(Core_ARM11, "swapping M <-> N"); 870 LOG_TRACE(Core_ARM, "swapping M <-> N");
871 } 871 }
872 872
873 vsd->sign = vsn->sign ^ vsm->sign; 873 vsd->sign = vsn->sign ^ vsm->sign;
@@ -919,7 +919,7 @@ static u32 vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s3
919 s32 v; 919 s32 v;
920 920
921 v = vfp_get_float(state, sn); 921 v = vfp_get_float(state, sn);
922 LOG_TRACE(Core_ARM11, "s%u = %08x", sn, v); 922 LOG_TRACE(Core_ARM, "s%u = %08x", sn, v);
923 exceptions |= vfp_single_unpack(&vsn, v, fpscr); 923 exceptions |= vfp_single_unpack(&vsn, v, fpscr);
924 if (vsn.exponent == 0 && vsn.significand) 924 if (vsn.exponent == 0 && vsn.significand)
925 vfp_single_normalise_denormal(&vsn); 925 vfp_single_normalise_denormal(&vsn);
@@ -934,7 +934,7 @@ static u32 vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s3
934 vsp.sign = vfp_sign_negate(vsp.sign); 934 vsp.sign = vfp_sign_negate(vsp.sign);
935 935
936 v = vfp_get_float(state, sd); 936 v = vfp_get_float(state, sd);
937 LOG_TRACE(Core_ARM11, "s%u = %08x", sd, v); 937 LOG_TRACE(Core_ARM, "s%u = %08x", sd, v);
938 exceptions |= vfp_single_unpack(&vsn, v, fpscr); 938 exceptions |= vfp_single_unpack(&vsn, v, fpscr);
939 if (vsn.exponent == 0 && vsn.significand != 0) 939 if (vsn.exponent == 0 && vsn.significand != 0)
940 vfp_single_normalise_denormal(&vsn); 940 vfp_single_normalise_denormal(&vsn);
@@ -955,7 +955,7 @@ static u32 vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s3
955 * sd = sd + (sn * sm) 955 * sd = sd + (sn * sm)
956 */ 956 */
957static u32 vfp_single_fmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { 957static u32 vfp_single_fmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
958 LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd); 958 LOG_TRACE(Core_ARM, "s%u = %08x", sn, sd);
959 return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, 0, "fmac"); 959 return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, 0, "fmac");
960} 960}
961 961
@@ -964,7 +964,7 @@ static u32 vfp_single_fmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
964 */ 964 */
965static u32 vfp_single_fnmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { 965static u32 vfp_single_fnmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
966 // TODO: this one has its arguments inverted, investigate. 966 // TODO: this one has its arguments inverted, investigate.
967 LOG_TRACE(Core_ARM11, "s%u = %08x", sd, sn); 967 LOG_TRACE(Core_ARM, "s%u = %08x", sd, sn);
968 return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_MULTIPLY, "fnmac"); 968 return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_MULTIPLY, "fnmac");
969} 969}
970 970
@@ -972,7 +972,7 @@ static u32 vfp_single_fnmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr
972 * sd = -sd + (sn * sm) 972 * sd = -sd + (sn * sm)
973 */ 973 */
974static u32 vfp_single_fmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { 974static u32 vfp_single_fmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
975 LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd); 975 LOG_TRACE(Core_ARM, "s%u = %08x", sn, sd);
976 return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_SUBTRACT, "fmsc"); 976 return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_SUBTRACT, "fmsc");
977} 977}
978 978
@@ -980,7 +980,7 @@ static u32 vfp_single_fmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
980 * sd = -sd - (sn * sm) 980 * sd = -sd - (sn * sm)
981 */ 981 */
982static u32 vfp_single_fnmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { 982static u32 vfp_single_fnmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
983 LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd); 983 LOG_TRACE(Core_ARM, "s%u = %08x", sn, sd);
984 return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, 984 return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_SUBTRACT | NEG_MULTIPLY,
985 "fnmsc"); 985 "fnmsc");
986} 986}
@@ -993,7 +993,7 @@ static u32 vfp_single_fmul(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
993 u32 exceptions = 0; 993 u32 exceptions = 0;
994 s32 n = vfp_get_float(state, sn); 994 s32 n = vfp_get_float(state, sn);
995 995
996 LOG_TRACE(Core_ARM11, "s%u = %08x", sn, n); 996 LOG_TRACE(Core_ARM, "s%u = %08x", sn, n);
997 997
998 exceptions |= vfp_single_unpack(&vsn, n, fpscr); 998 exceptions |= vfp_single_unpack(&vsn, n, fpscr);
999 if (vsn.exponent == 0 && vsn.significand) 999 if (vsn.exponent == 0 && vsn.significand)
@@ -1015,7 +1015,7 @@ static u32 vfp_single_fnmul(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr
1015 u32 exceptions = 0; 1015 u32 exceptions = 0;
1016 s32 n = vfp_get_float(state, sn); 1016 s32 n = vfp_get_float(state, sn);
1017 1017
1018 LOG_TRACE(Core_ARM11, "s%u = %08x", sn, n); 1018 LOG_TRACE(Core_ARM, "s%u = %08x", sn, n);
1019 1019
1020 exceptions |= vfp_single_unpack(&vsn, n, fpscr); 1020 exceptions |= vfp_single_unpack(&vsn, n, fpscr);
1021 if (vsn.exponent == 0 && vsn.significand) 1021 if (vsn.exponent == 0 && vsn.significand)
@@ -1038,7 +1038,7 @@ static u32 vfp_single_fadd(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
1038 u32 exceptions = 0; 1038 u32 exceptions = 0;
1039 s32 n = vfp_get_float(state, sn); 1039 s32 n = vfp_get_float(state, sn);
1040 1040
1041 LOG_TRACE(Core_ARM11, "s%u = %08x", sn, n); 1041 LOG_TRACE(Core_ARM, "s%u = %08x", sn, n);
1042 1042
1043 /* 1043 /*
1044 * Unpack and normalise denormals. 1044 * Unpack and normalise denormals.
@@ -1060,7 +1060,7 @@ static u32 vfp_single_fadd(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
1060 * sd = sn - sm 1060 * sd = sn - sm
1061 */ 1061 */
1062static u32 vfp_single_fsub(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { 1062static u32 vfp_single_fsub(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
1063 LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd); 1063 LOG_TRACE(Core_ARM, "s%u = %08x", sn, sd);
1064 /* 1064 /*
1065 * Subtraction is addition with one sign inverted. Unpack the second operand to perform FTZ if 1065 * Subtraction is addition with one sign inverted. Unpack the second operand to perform FTZ if
1066 * necessary, we can't let fadd do this because a denormal in m might get flushed to +0 in FTZ 1066 * necessary, we can't let fadd do this because a denormal in m might get flushed to +0 in FTZ
@@ -1089,7 +1089,7 @@ static u32 vfp_single_fdiv(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
1089 s32 n = vfp_get_float(state, sn); 1089 s32 n = vfp_get_float(state, sn);
1090 int tm, tn; 1090 int tm, tn;
1091 1091
1092 LOG_TRACE(Core_ARM11, "s%u = %08x", sn, n); 1092 LOG_TRACE(Core_ARM, "s%u = %08x", sn, n);
1093 1093
1094 exceptions |= vfp_single_unpack(&vsn, n, fpscr); 1094 exceptions |= vfp_single_unpack(&vsn, n, fpscr);
1095 exceptions |= vfp_single_unpack(&vsm, m, fpscr); 1095 exceptions |= vfp_single_unpack(&vsm, m, fpscr);
@@ -1229,10 +1229,10 @@ u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr) {
1229 else 1229 else
1230 veclen = fpscr & FPSCR_LENGTH_MASK; 1230 veclen = fpscr & FPSCR_LENGTH_MASK;
1231 1231
1232 LOG_TRACE(Core_ARM11, "vecstride=%u veclen=%u", vecstride, (veclen >> FPSCR_LENGTH_BIT) + 1); 1232 LOG_TRACE(Core_ARM, "vecstride=%u veclen=%u", vecstride, (veclen >> FPSCR_LENGTH_BIT) + 1);
1233 1233
1234 if (!fop->fn) { 1234 if (!fop->fn) {
1235 LOG_CRITICAL(Core_ARM11, "could not find single op %d, inst=0x%x@0x%x", FEXT_TO_IDX(inst), 1235 LOG_CRITICAL(Core_ARM, "could not find single op %d, inst=0x%x@0x%x", FEXT_TO_IDX(inst),
1236 inst, state->Reg[15]); 1236 inst, state->Reg[15]);
1237 Crash(); 1237 Crash();
1238 goto invalid; 1238 goto invalid;
@@ -1245,14 +1245,14 @@ u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr) {
1245 1245
1246 type = (fop->flags & OP_DD) ? 'd' : 's'; 1246 type = (fop->flags & OP_DD) ? 'd' : 's';
1247 if (op == FOP_EXT) 1247 if (op == FOP_EXT)
1248 LOG_TRACE(Core_ARM11, "itr%d (%c%u) = op[%u] (s%u=%08x)", vecitr >> FPSCR_LENGTH_BIT, 1248 LOG_TRACE(Core_ARM, "itr%d (%c%u) = op[%u] (s%u=%08x)", vecitr >> FPSCR_LENGTH_BIT,
1249 type, dest, sn, sm, m); 1249 type, dest, sn, sm, m);
1250 else 1250 else
1251 LOG_TRACE(Core_ARM11, "itr%d (%c%u) = (s%u) op[%u] (s%u=%08x)", 1251 LOG_TRACE(Core_ARM, "itr%d (%c%u) = (s%u) op[%u] (s%u=%08x)",
1252 vecitr >> FPSCR_LENGTH_BIT, type, dest, sn, FOP_TO_IDX(op), sm, m); 1252 vecitr >> FPSCR_LENGTH_BIT, type, dest, sn, FOP_TO_IDX(op), sm, m);
1253 1253
1254 except = fop->fn(state, dest, sn, m, fpscr); 1254 except = fop->fn(state, dest, sn, m, fpscr);
1255 LOG_TRACE(Core_ARM11, "itr%d: exceptions=%08x", vecitr >> FPSCR_LENGTH_BIT, except); 1255 LOG_TRACE(Core_ARM, "itr%d: exceptions=%08x", vecitr >> FPSCR_LENGTH_BIT, except);
1256 1256
1257 exceptions |= except & ~VFP_NAN_FLAG; 1257 exceptions |= except & ~VFP_NAN_FLAG;
1258 1258
diff --git a/src/core/core.cpp b/src/core/core.cpp
index c5448630f..6358e827b 100644
--- a/src/core/core.cpp
+++ b/src/core/core.cpp
@@ -52,7 +52,7 @@ System::ResultStatus System::RunLoop(int tight_loop) {
52 // If we don't have a currently active thread then don't execute instructions, 52 // If we don't have a currently active thread then don't execute instructions,
53 // instead advance to the next event and try to yield to the next thread 53 // instead advance to the next event and try to yield to the next thread
54 if (Kernel::GetCurrentThread() == nullptr) { 54 if (Kernel::GetCurrentThread() == nullptr) {
55 LOG_TRACE(Core_ARM11, "Idling"); 55 LOG_TRACE(Core_ARM, "Idling");
56 CoreTiming::Idle(); 56 CoreTiming::Idle();
57 CoreTiming::Advance(); 57 CoreTiming::Advance();
58 PrepareReschedule(); 58 PrepareReschedule();