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| author | 2021-04-11 20:54:51 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:27 -0400 | |
| commit | 415c7e46ed2f00bb4611cf2913eac1b92ca130bc (patch) | |
| tree | 8c85f3090341ba51806f474666020b97ceecd1ce /src | |
| parent | shader: Mark blocks with no end branch as unreachable (diff) | |
| download | yuzu-415c7e46ed2f00bb4611cf2913eac1b92ca130bc.tar.gz yuzu-415c7e46ed2f00bb4611cf2913eac1b92ca130bc.tar.xz yuzu-415c7e46ed2f00bb4611cf2913eac1b92ca130bc.zip | |
shader: Simplify FLO and throw on CC
Diffstat (limited to 'src')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp index d5361bec5..f0cb25d61 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp | |||
| @@ -8,26 +8,27 @@ | |||
| 8 | 8 | ||
| 9 | namespace Shader::Maxwell { | 9 | namespace Shader::Maxwell { |
| 10 | namespace { | 10 | namespace { |
| 11 | void FLO(TranslatorVisitor& v, u64 insn, const IR::U32& src) { | 11 | void FLO(TranslatorVisitor& v, u64 insn, IR::U32 src) { |
| 12 | union { | 12 | union { |
| 13 | u64 insn; | 13 | u64 insn; |
| 14 | BitField<0, 8, IR::Reg> dest_reg; | 14 | BitField<0, 8, IR::Reg> dest_reg; |
| 15 | BitField<40, 1, u64> tilde; | 15 | BitField<40, 1, u64> tilde; |
| 16 | BitField<41, 1, u64> shift; | 16 | BitField<41, 1, u64> shift; |
| 17 | BitField<47, 1, u64> cc; | ||
| 17 | BitField<48, 1, u64> is_signed; | 18 | BitField<48, 1, u64> is_signed; |
| 18 | } const flo{insn}; | 19 | } const flo{insn}; |
| 19 | 20 | ||
| 20 | const bool invert{flo.tilde != 0}; | 21 | if (flo.cc != 0) { |
| 21 | const bool is_signed{flo.is_signed != 0}; | 22 | throw NotImplementedException("CC"); |
| 22 | const bool shift_op{flo.shift != 0}; | 23 | } |
| 23 | 24 | if (flo.tilde != 0) { | |
| 24 | const IR::U32 operand{invert ? v.ir.BitwiseNot(src) : src}; | 25 | src = v.ir.BitwiseNot(src); |
| 25 | const IR::U32 find_result{is_signed ? v.ir.FindSMsb(operand) : v.ir.FindUMsb(operand)}; | 26 | } |
| 26 | const IR::U1 find_fail{v.ir.IEqual(find_result, v.ir.Imm32(-1))}; | 27 | IR::U32 result{flo.is_signed != 0 ? v.ir.FindSMsb(src) : v.ir.FindUMsb(src)}; |
| 27 | const IR::U32 offset{v.ir.Imm32(31)}; | 28 | if (flo.shift != 0) { |
| 28 | const IR::U32 success_result{shift_op ? IR::U32{v.ir.ISub(offset, find_result)} : find_result}; | 29 | const IR::U1 not_found{v.ir.IEqual(result, v.ir.Imm32(-1))}; |
| 29 | 30 | result = IR::U32{v.ir.Select(not_found, result, v.ir.BitwiseXor(result, v.ir.Imm32(31)))}; | |
| 30 | const IR::U32 result{v.ir.Select(find_fail, find_result, success_result)}; | 31 | } |
| 31 | v.X(flo.dest_reg, result); | 32 | v.X(flo.dest_reg, result); |
| 32 | } | 33 | } |
| 33 | } // Anonymous namespace | 34 | } // Anonymous namespace |