diff options
| author | 2015-03-08 21:53:03 -0400 | |
|---|---|---|
| committer | 2015-03-08 22:03:11 -0400 | |
| commit | 386dbab5ea5bd8503471dc010346a9c1b715df23 (patch) | |
| tree | a97be6f0cdc394f9ee00b7d002d1472d8847f22b /src | |
| parent | dyncom: General cleanup of STM (diff) | |
| download | yuzu-386dbab5ea5bd8503471dc010346a9c1b715df23.tar.gz yuzu-386dbab5ea5bd8503471dc010346a9c1b715df23.tar.xz yuzu-386dbab5ea5bd8503471dc010346a9c1b715df23.zip | |
dyncom: Fix an indexing bug in STM
Previously it would write the contents of register 13 for the case where the link register (r14) is supposed to be written.
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index ba09c58b7..2f72f5077 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |||
| @@ -5976,13 +5976,12 @@ unsigned InterpreterMainLoop(ARMul_State* state) { | |||
| 5976 | ldst_inst* inst_cream = (ldst_inst*)inst_base->component; | 5976 | ldst_inst* inst_cream = (ldst_inst*)inst_base->component; |
| 5977 | unsigned int inst = inst_cream->inst; | 5977 | unsigned int inst = inst_cream->inst; |
| 5978 | 5978 | ||
| 5979 | int i; | ||
| 5980 | unsigned int Rn = BITS(inst, 16, 19); | 5979 | unsigned int Rn = BITS(inst, 16, 19); |
| 5981 | unsigned int old_RN = cpu->Reg[Rn]; | 5980 | unsigned int old_RN = cpu->Reg[Rn]; |
| 5982 | 5981 | ||
| 5983 | inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); | 5982 | inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); |
| 5984 | if (BIT(inst_cream->inst, 22) == 1) { | 5983 | if (BIT(inst_cream->inst, 22) == 1) { |
| 5985 | for (i = 0; i < 13; i++) { | 5984 | for (int i = 0; i < 13; i++) { |
| 5986 | if (BIT(inst_cream->inst, i)) { | 5985 | if (BIT(inst_cream->inst, i)) { |
| 5987 | Memory::Write32(addr, cpu->Reg[i]); | 5986 | Memory::Write32(addr, cpu->Reg[i]); |
| 5988 | addr += 4; | 5987 | addr += 4; |
| @@ -5990,7 +5989,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { | |||
| 5990 | } | 5989 | } |
| 5991 | if (BIT(inst_cream->inst, 13)) { | 5990 | if (BIT(inst_cream->inst, 13)) { |
| 5992 | if (cpu->Mode == USER32MODE) | 5991 | if (cpu->Mode == USER32MODE) |
| 5993 | Memory::Write32(addr, cpu->Reg[i]); | 5992 | Memory::Write32(addr, cpu->Reg[13]); |
| 5994 | else | 5993 | else |
| 5995 | Memory::Write32(addr, cpu->Reg_usr[0]); | 5994 | Memory::Write32(addr, cpu->Reg_usr[0]); |
| 5996 | 5995 | ||
| @@ -5998,7 +5997,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { | |||
| 5998 | } | 5997 | } |
| 5999 | if (BIT(inst_cream->inst, 14)) { | 5998 | if (BIT(inst_cream->inst, 14)) { |
| 6000 | if (cpu->Mode == USER32MODE) | 5999 | if (cpu->Mode == USER32MODE) |
| 6001 | Memory::Write32(addr, cpu->Reg[i]); | 6000 | Memory::Write32(addr, cpu->Reg[14]); |
| 6002 | else | 6001 | else |
| 6003 | Memory::Write32(addr, cpu->Reg_usr[1]); | 6002 | Memory::Write32(addr, cpu->Reg_usr[1]); |
| 6004 | 6003 | ||
| @@ -6008,7 +6007,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { | |||
| 6008 | Memory::Write32(addr, cpu->Reg_usr[1] + 8); | 6007 | Memory::Write32(addr, cpu->Reg_usr[1] + 8); |
| 6009 | } | 6008 | } |
| 6010 | } else { | 6009 | } else { |
| 6011 | for (i = 0; i < 15; i++) { | 6010 | for (int i = 0; i < 15; i++) { |
| 6012 | if (BIT(inst_cream->inst, i)) { | 6011 | if (BIT(inst_cream->inst, i)) { |
| 6013 | if (i == Rn) | 6012 | if (i == Rn) |
| 6014 | Memory::Write32(addr, old_RN); | 6013 | Memory::Write32(addr, old_RN); |