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| author | 2018-07-21 23:13:27 -0700 | |
|---|---|---|
| committer | 2018-07-21 23:13:27 -0700 | |
| commit | 2d563ec8d5d5d7039e18725b016f31c4d871b6d9 (patch) | |
| tree | ac7bbe1cee0389d747518e3f520fa8e0a644242f /src | |
| parent | Merge pull request #764 from lioncash/move (diff) | |
| parent | gl_shader_decompiler: Implement SEL instruction. (diff) | |
| download | yuzu-2d563ec8d5d5d7039e18725b016f31c4d871b6d9.tar.gz yuzu-2d563ec8d5d5d7039e18725b016f31c4d871b6d9.tar.xz yuzu-2d563ec8d5d5d7039e18725b016f31c4d871b6d9.zip | |
Merge pull request #766 from bunnei/shader-sel
gl_shader_decompiler: Implement SEL instruction.
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 11 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 9 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 939a71022..f495b623b 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -290,6 +290,11 @@ union Instruction { | |||
| 290 | 290 | ||
| 291 | union { | 291 | union { |
| 292 | BitField<39, 3, u64> pred; | 292 | BitField<39, 3, u64> pred; |
| 293 | BitField<42, 1, u64> neg_pred; | ||
| 294 | } sel; | ||
| 295 | |||
| 296 | union { | ||
| 297 | BitField<39, 3, u64> pred; | ||
| 293 | BitField<42, 1, u64> negate_pred; | 298 | BitField<42, 1, u64> negate_pred; |
| 294 | BitField<43, 2, IMinMaxExchange> exchange; | 299 | BitField<43, 2, IMinMaxExchange> exchange; |
| 295 | BitField<48, 1, u64> is_signed; | 300 | BitField<48, 1, u64> is_signed; |
| @@ -513,6 +518,9 @@ public: | |||
| 513 | ISCADD_C, // Scale and Add | 518 | ISCADD_C, // Scale and Add |
| 514 | ISCADD_R, | 519 | ISCADD_R, |
| 515 | ISCADD_IMM, | 520 | ISCADD_IMM, |
| 521 | SEL_C, | ||
| 522 | SEL_R, | ||
| 523 | SEL_IMM, | ||
| 516 | MUFU, // Multi-Function Operator | 524 | MUFU, // Multi-Function Operator |
| 517 | RRO_C, // Range Reduction Operator | 525 | RRO_C, // Range Reduction Operator |
| 518 | RRO_R, | 526 | RRO_R, |
| @@ -713,6 +721,9 @@ private: | |||
| 713 | INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"), | 721 | INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"), |
| 714 | INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"), | 722 | INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"), |
| 715 | INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"), | 723 | INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"), |
| 724 | INST("0100110010100---", Id::SEL_C, Type::ArithmeticInteger, "SEL_C"), | ||
| 725 | INST("0101110010100---", Id::SEL_R, Type::ArithmeticInteger, "SEL_R"), | ||
| 726 | INST("0011100010100---", Id::SEL_IMM, Type::ArithmeticInteger, "SEL_IMM"), | ||
| 716 | INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), | 727 | INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), |
| 717 | INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), | 728 | INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), |
| 718 | INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), | 729 | INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), |
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index b48d30466..bfbfc3ac2 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -1139,6 +1139,15 @@ private: | |||
| 1139 | "((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1); | 1139 | "((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1); |
| 1140 | break; | 1140 | break; |
| 1141 | } | 1141 | } |
| 1142 | case OpCode::Id::SEL_C: | ||
| 1143 | case OpCode::Id::SEL_R: | ||
| 1144 | case OpCode::Id::SEL_IMM: { | ||
| 1145 | std::string condition = | ||
| 1146 | GetPredicateCondition(instr.sel.pred, instr.sel.neg_pred != 0); | ||
| 1147 | regs.SetRegisterToInteger(instr.gpr0, true, 0, | ||
| 1148 | '(' + condition + ") ? " + op_a + " : " + op_b, 1, 1); | ||
| 1149 | break; | ||
| 1150 | } | ||
| 1142 | case OpCode::Id::LOP_C: | 1151 | case OpCode::Id::LOP_C: |
| 1143 | case OpCode::Id::LOP_R: | 1152 | case OpCode::Id::LOP_R: |
| 1144 | case OpCode::Id::LOP_IMM: { | 1153 | case OpCode::Id::LOP_IMM: { |