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| author | 2018-08-20 14:31:33 -0400 | |
|---|---|---|
| committer | 2018-08-20 14:31:33 -0400 | |
| commit | 296e57fa0e0cd681b8063560c9c9ca60cfb77889 (patch) | |
| tree | 44887a9f0edb41795b7eedf8b268887b611df89b /src | |
| parent | Merge pull request #1112 from Subv/sampler_types (diff) | |
| parent | Shaders/TEXS: Fixed the component mask in the TEXS instruction. (diff) | |
| download | yuzu-296e57fa0e0cd681b8063560c9c9ca60cfb77889.tar.gz yuzu-296e57fa0e0cd681b8063560c9c9ca60cfb77889.tar.xz yuzu-296e57fa0e0cd681b8063560c9c9ca60cfb77889.zip | |
Merge pull request #1115 from Subv/texs_mask
Shaders/TEXS: Write to the correct output register when swizzling.
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index f3b2d1328..ac6ccfec7 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -840,29 +840,29 @@ private: | |||
| 840 | ++shader.scope; | 840 | ++shader.scope; |
| 841 | shader.AddLine(coord); | 841 | shader.AddLine(coord); |
| 842 | 842 | ||
| 843 | // TEXS has two destination registers. RG goes into gpr0+0 and gpr0+1, and BA | 843 | // TEXS has two destination registers and a swizzle. The first two elements in the swizzle |
| 844 | // goes into gpr28+0 and gpr28+1 | 844 | // go into gpr0+0 and gpr0+1, and the rest goes into gpr28+0 and gpr28+1 |
| 845 | size_t texs_offset{}; | 845 | |
| 846 | 846 | size_t written_components = 0; | |
| 847 | size_t src_elem{}; | 847 | for (u32 component = 0; component < 4; ++component) { |
| 848 | for (const auto& dest : {instr.gpr0.Value(), instr.gpr28.Value()}) { | 848 | if (!instr.texs.IsComponentEnabled(component)) { |
| 849 | size_t dest_elem{}; | 849 | continue; |
| 850 | for (unsigned elem = 0; elem < 2; ++elem) { | ||
| 851 | if (!instr.texs.IsComponentEnabled(src_elem++)) { | ||
| 852 | // Skip disabled components | ||
| 853 | continue; | ||
| 854 | } | ||
| 855 | regs.SetRegisterToFloat(dest, elem + texs_offset, texture, 1, 4, false, | ||
| 856 | dest_elem++); | ||
| 857 | } | 850 | } |
| 858 | 851 | ||
| 859 | if (!instr.texs.HasTwoDestinations()) { | 852 | if (written_components < 2) { |
| 860 | // Skip the second destination | 853 | // Write the first two swizzle components to gpr0 and gpr0+1 |
| 861 | break; | 854 | regs.SetRegisterToFloat(instr.gpr0, component, texture, 1, 4, false, |
| 855 | written_components % 2); | ||
| 856 | } else { | ||
| 857 | ASSERT(instr.texs.HasTwoDestinations()); | ||
| 858 | // Write the rest of the swizzle components to gpr28 and gpr28+1 | ||
| 859 | regs.SetRegisterToFloat(instr.gpr28, component, texture, 1, 4, false, | ||
| 860 | written_components % 2); | ||
| 862 | } | 861 | } |
| 863 | 862 | ||
| 864 | texs_offset += 2; | 863 | ++written_components; |
| 865 | } | 864 | } |
| 865 | |||
| 866 | --shader.scope; | 866 | --shader.scope; |
| 867 | shader.AddLine('}'); | 867 | shader.AddLine('}'); |
| 868 | } | 868 | } |