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authorGravatar bunnei2018-04-21 12:31:30 -0400
committerGravatar bunnei2018-04-24 17:49:19 -0400
commit239ac8abe228b9080741ba7d50d9e13cc4a1ceae (patch)
tree14b6df493ec5ff15faf2c7b71e45fe7d8ebb53df /src
parentmemory_manager: Use GPUVAdddr, not PAddr, for GPU addresses. (diff)
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memory_manager: Make GpuToCpuAddress return an optional.
Diffstat (limited to 'src')
-rw-r--r--src/video_core/command_processor.cpp6
-rw-r--r--src/video_core/engines/maxwell_3d.cpp21
-rw-r--r--src/video_core/memory_manager.cpp7
-rw-r--r--src/video_core/memory_manager.h5
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer.cpp14
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer_cache.cpp4
-rw-r--r--src/yuzu/debugger/graphics/graphics_surface.cpp8
7 files changed, 37 insertions, 28 deletions
diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index 7850ae103..2c04daba3 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -90,9 +90,9 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
90} 90}
91 91
92void GPU::ProcessCommandList(GPUVAddr address, u32 size) { 92void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
93 const VAddr head_address = memory_manager->GpuToCpuAddress(address); 93 const boost::optional<VAddr> head_address = memory_manager->GpuToCpuAddress(address);
94 VAddr current_addr = head_address; 94 VAddr current_addr = *head_address;
95 while (current_addr < head_address + size * sizeof(CommandHeader)) { 95 while (current_addr < *head_address + size * sizeof(CommandHeader)) {
96 const CommandHeader header = {Memory::Read32(current_addr)}; 96 const CommandHeader header = {Memory::Read32(current_addr)};
97 current_addr += sizeof(u32); 97 current_addr += sizeof(u32);
98 98
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 8d7d627b8..4e9aed380 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -145,7 +145,7 @@ void Maxwell3D::ProcessQueryGet() {
145 GPUVAddr sequence_address = regs.query.QueryAddress(); 145 GPUVAddr sequence_address = regs.query.QueryAddress();
146 // Since the sequence address is given as a GPU VAddr, we have to convert it to an application 146 // Since the sequence address is given as a GPU VAddr, we have to convert it to an application
147 // VAddr before writing. 147 // VAddr before writing.
148 VAddr address = memory_manager.GpuToCpuAddress(sequence_address); 148 boost::optional<VAddr> address = memory_manager.GpuToCpuAddress(sequence_address);
149 149
150 // TODO(Subv): Support the other query units. 150 // TODO(Subv): Support the other query units.
151 ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop, 151 ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
@@ -153,7 +153,7 @@ void Maxwell3D::ProcessQueryGet() {
153 ASSERT_MSG(regs.query.query_get.short_query, 153 ASSERT_MSG(regs.query.query_get.short_query,
154 "Writing the entire query result structure is unimplemented"); 154 "Writing the entire query result structure is unimplemented");
155 155
156 u32 value = Memory::Read32(address); 156 u32 value = Memory::Read32(*address);
157 u32 result = 0; 157 u32 result = 0;
158 158
159 // TODO(Subv): Support the other query variables 159 // TODO(Subv): Support the other query variables
@@ -173,7 +173,7 @@ void Maxwell3D::ProcessQueryGet() {
173 case Regs::QueryMode::Write2: { 173 case Regs::QueryMode::Write2: {
174 // Write the current query sequence to the sequence address. 174 // Write the current query sequence to the sequence address.
175 u32 sequence = regs.query.query_sequence; 175 u32 sequence = regs.query.query_sequence;
176 Memory::Write32(address, sequence); 176 Memory::Write32(*address, sequence);
177 177
178 // TODO(Subv): Write the proper query response structure to the address when not using short 178 // TODO(Subv): Write the proper query response structure to the address when not using short
179 // mode. 179 // mode.
@@ -225,9 +225,10 @@ void Maxwell3D::ProcessCBData(u32 value) {
225 // Don't allow writing past the end of the buffer. 225 // Don't allow writing past the end of the buffer.
226 ASSERT(regs.const_buffer.cb_pos + sizeof(u32) <= regs.const_buffer.cb_size); 226 ASSERT(regs.const_buffer.cb_pos + sizeof(u32) <= regs.const_buffer.cb_size);
227 227
228 VAddr address = memory_manager.GpuToCpuAddress(buffer_address + regs.const_buffer.cb_pos); 228 boost::optional<VAddr> address =
229 memory_manager.GpuToCpuAddress(buffer_address + regs.const_buffer.cb_pos);
229 230
230 Memory::Write32(address, value); 231 Memory::Write32(*address, value);
231 232
232 // Increment the current buffer position. 233 // Increment the current buffer position.
233 regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4; 234 regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4;
@@ -237,10 +238,10 @@ Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
237 GPUVAddr tic_base_address = regs.tic.TICAddress(); 238 GPUVAddr tic_base_address = regs.tic.TICAddress();
238 239
239 GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry); 240 GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry);
240 VAddr tic_address_cpu = memory_manager.GpuToCpuAddress(tic_address_gpu); 241 boost::optional<VAddr> tic_address_cpu = memory_manager.GpuToCpuAddress(tic_address_gpu);
241 242
242 Texture::TICEntry tic_entry; 243 Texture::TICEntry tic_entry;
243 Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry)); 244 Memory::ReadBlock(*tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
244 245
245 ASSERT_MSG(tic_entry.header_version == Texture::TICHeaderVersion::BlockLinear || 246 ASSERT_MSG(tic_entry.header_version == Texture::TICHeaderVersion::BlockLinear ||
246 tic_entry.header_version == Texture::TICHeaderVersion::Pitch, 247 tic_entry.header_version == Texture::TICHeaderVersion::Pitch,
@@ -267,10 +268,10 @@ Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const {
267 GPUVAddr tsc_base_address = regs.tsc.TSCAddress(); 268 GPUVAddr tsc_base_address = regs.tsc.TSCAddress();
268 269
269 GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry); 270 GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry);
270 VAddr tsc_address_cpu = memory_manager.GpuToCpuAddress(tsc_address_gpu); 271 boost::optional<VAddr> tsc_address_cpu = memory_manager.GpuToCpuAddress(tsc_address_gpu);
271 272
272 Texture::TSCEntry tsc_entry; 273 Texture::TSCEntry tsc_entry;
273 Memory::ReadBlock(tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry)); 274 Memory::ReadBlock(*tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry));
274 return tsc_entry; 275 return tsc_entry;
275} 276}
276 277
@@ -292,7 +293,7 @@ std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderSt
292 current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) { 293 current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) {
293 294
294 Texture::TextureHandle tex_handle{ 295 Texture::TextureHandle tex_handle{
295 Memory::Read32(memory_manager.GpuToCpuAddress(current_texture))}; 296 Memory::Read32(*memory_manager.GpuToCpuAddress(current_texture))};
296 297
297 Texture::FullTextureInfo tex_info{}; 298 Texture::FullTextureInfo tex_info{};
298 // TODO(Subv): Use the shader to determine which textures are actually accessed. 299 // TODO(Subv): Use the shader to determine which textures are actually accessed.
diff --git a/src/video_core/memory_manager.cpp b/src/video_core/memory_manager.cpp
index 3f21071c0..9bbbb7e65 100644
--- a/src/video_core/memory_manager.cpp
+++ b/src/video_core/memory_manager.cpp
@@ -73,9 +73,14 @@ boost::optional<GPUVAddr> MemoryManager::FindFreeBlock(u64 size, u64 align) {
73 return {}; 73 return {};
74} 74}
75 75
76VAddr MemoryManager::GpuToCpuAddress(GPUVAddr gpu_addr) { 76boost::optional<VAddr> MemoryManager::GpuToCpuAddress(GPUVAddr gpu_addr) {
77 VAddr base_addr = PageSlot(gpu_addr); 77 VAddr base_addr = PageSlot(gpu_addr);
78 ASSERT(base_addr != static_cast<u64>(PageStatus::Unmapped)); 78 ASSERT(base_addr != static_cast<u64>(PageStatus::Unmapped));
79
80 if (base_addr == static_cast<u64>(PageStatus::Allocated)) {
81 return {};
82 }
83
79 return base_addr + (gpu_addr & PAGE_MASK); 84 return base_addr + (gpu_addr & PAGE_MASK);
80} 85}
81 86
diff --git a/src/video_core/memory_manager.h b/src/video_core/memory_manager.h
index 4710cb21f..246c8fb7e 100644
--- a/src/video_core/memory_manager.h
+++ b/src/video_core/memory_manager.h
@@ -6,6 +6,9 @@
6 6
7#include <array> 7#include <array>
8#include <memory> 8#include <memory>
9
10#include <boost/optional.hpp>
11
9#include "common/common_types.h" 12#include "common/common_types.h"
10#include "core/memory.h" 13#include "core/memory.h"
11 14
@@ -22,7 +25,7 @@ public:
22 GPUVAddr AllocateSpace(GPUVAddr gpu_addr, u64 size, u64 align); 25 GPUVAddr AllocateSpace(GPUVAddr gpu_addr, u64 size, u64 align);
23 GPUVAddr MapBufferEx(VAddr cpu_addr, u64 size); 26 GPUVAddr MapBufferEx(VAddr cpu_addr, u64 size);
24 GPUVAddr MapBufferEx(VAddr cpu_addr, GPUVAddr gpu_addr, u64 size); 27 GPUVAddr MapBufferEx(VAddr cpu_addr, GPUVAddr gpu_addr, u64 size);
25 VAddr GpuToCpuAddress(GPUVAddr gpu_addr); 28 boost::optional<VAddr> GpuToCpuAddress(GPUVAddr gpu_addr);
26 29
27 static constexpr u64 PAGE_BITS = 16; 30 static constexpr u64 PAGE_BITS = 16;
28 static constexpr u64 PAGE_SIZE = 1 << PAGE_BITS; 31 static constexpr u64 PAGE_SIZE = 1 << PAGE_BITS;
diff --git a/src/video_core/renderer_opengl/gl_rasterizer.cpp b/src/video_core/renderer_opengl/gl_rasterizer.cpp
index 8568d6762..71612790b 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer.cpp
@@ -150,7 +150,7 @@ std::pair<u8*, GLintptr> RasterizerOpenGL::SetupVertexArrays(u8* array_ptr,
150 u64 size = end - start + 1; 150 u64 size = end - start + 1;
151 151
152 // Copy vertex array data 152 // Copy vertex array data
153 const VAddr data_addr{memory_manager->PhysicalToVirtualAddress(start)}; 153 const VAddr data_addr{*memory_manager->GpuToCpuAddress(start)};
154 res_cache.FlushRegion(data_addr, size, nullptr); 154 res_cache.FlushRegion(data_addr, size, nullptr);
155 Memory::ReadBlock(data_addr, array_ptr, size); 155 Memory::ReadBlock(data_addr, array_ptr, size);
156 156
@@ -233,8 +233,8 @@ void RasterizerOpenGL::SetupShaders(u8* buffer_ptr, GLintptr buffer_offset) {
233 // Fetch program code from memory 233 // Fetch program code from memory
234 GLShader::ProgramCode program_code; 234 GLShader::ProgramCode program_code;
235 const u64 gpu_address{gpu.regs.code_address.CodeAddress() + shader_config.offset}; 235 const u64 gpu_address{gpu.regs.code_address.CodeAddress() + shader_config.offset};
236 const VAddr cpu_address{gpu.memory_manager.GpuToCpuAddress(gpu_address)}; 236 const boost::optional<VAddr> cpu_address{gpu.memory_manager.GpuToCpuAddress(gpu_address)};
237 Memory::ReadBlock(cpu_address, program_code.data(), program_code.size() * sizeof(u64)); 237 Memory::ReadBlock(*cpu_address, program_code.data(), program_code.size() * sizeof(u64));
238 GLShader::ShaderSetup setup{std::move(program_code)}; 238 GLShader::ShaderSetup setup{std::move(program_code)};
239 239
240 GLShader::ShaderEntries shader_resources; 240 GLShader::ShaderEntries shader_resources;
@@ -394,9 +394,9 @@ void RasterizerOpenGL::DrawArrays() {
394 GLintptr index_buffer_offset = 0; 394 GLintptr index_buffer_offset = 0;
395 if (is_indexed) { 395 if (is_indexed) {
396 const auto& memory_manager = Core::System().GetInstance().GPU().memory_manager; 396 const auto& memory_manager = Core::System().GetInstance().GPU().memory_manager;
397 const VAddr index_data_addr{ 397 const boost::optional<VAddr> index_data_addr{
398 memory_manager->GpuToCpuAddress(regs.index_array.StartAddress())}; 398 memory_manager->GpuToCpuAddress(regs.index_array.StartAddress())};
399 Memory::ReadBlock(index_data_addr, offseted_buffer, index_buffer_size); 399 Memory::ReadBlock(*index_data_addr, offseted_buffer, index_buffer_size);
400 400
401 index_buffer_offset = buffer_offset; 401 index_buffer_offset = buffer_offset;
402 offseted_buffer += index_buffer_size; 402 offseted_buffer += index_buffer_size;
@@ -659,9 +659,9 @@ u32 RasterizerOpenGL::SetupConstBuffers(Maxwell::ShaderStage stage, GLuint progr
659 buffer_draw_state.enabled = true; 659 buffer_draw_state.enabled = true;
660 buffer_draw_state.bindpoint = current_bindpoint + bindpoint; 660 buffer_draw_state.bindpoint = current_bindpoint + bindpoint;
661 661
662 VAddr addr = gpu.memory_manager->GpuToCpuAddress(buffer.address); 662 boost::optional<VAddr> addr = gpu.memory_manager->GpuToCpuAddress(buffer.address);
663 std::vector<u8> data(used_buffer.GetSize() * sizeof(float)); 663 std::vector<u8> data(used_buffer.GetSize() * sizeof(float));
664 Memory::ReadBlock(addr, data.data(), data.size()); 664 Memory::ReadBlock(*addr, data.data(), data.size());
665 665
666 glBindBuffer(GL_SHADER_STORAGE_BUFFER, buffer_draw_state.ssbo); 666 glBindBuffer(GL_SHADER_STORAGE_BUFFER, buffer_draw_state.ssbo);
667 glBufferData(GL_SHADER_STORAGE_BUFFER, data.size(), data.data(), GL_DYNAMIC_DRAW); 667 glBufferData(GL_SHADER_STORAGE_BUFFER, data.size(), data.data(), GL_DYNAMIC_DRAW);
diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
index 46f0f25aa..ced648c12 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
@@ -1028,7 +1028,7 @@ Surface RasterizerCacheOpenGL::GetTextureSurface(const Tegra::Texture::FullTextu
1028 auto& gpu = Core::System::GetInstance().GPU(); 1028 auto& gpu = Core::System::GetInstance().GPU();
1029 1029
1030 SurfaceParams params; 1030 SurfaceParams params;
1031 params.addr = gpu.memory_manager->GpuToCpuAddress(config.tic.Address()); 1031 params.addr = *gpu.memory_manager->GpuToCpuAddress(config.tic.Address());
1032 params.width = config.tic.Width(); 1032 params.width = config.tic.Width();
1033 params.height = config.tic.Height(); 1033 params.height = config.tic.Height();
1034 params.is_tiled = config.tic.IsTiled(); 1034 params.is_tiled = config.tic.IsTiled();
@@ -1106,7 +1106,7 @@ SurfaceSurfaceRect_Tuple RasterizerCacheOpenGL::GetFramebufferSurfaces(
1106 color_params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight; 1106 color_params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
1107 SurfaceParams depth_params = color_params; 1107 SurfaceParams depth_params = color_params;
1108 1108
1109 color_params.addr = memory_manager->GpuToCpuAddress(config.Address()); 1109 color_params.addr = *memory_manager->GpuToCpuAddress(config.Address());
1110 color_params.pixel_format = SurfaceParams::PixelFormatFromRenderTargetFormat(config.format); 1110 color_params.pixel_format = SurfaceParams::PixelFormatFromRenderTargetFormat(config.format);
1111 color_params.component_type = SurfaceParams::ComponentTypeFromRenderTarget(config.format); 1111 color_params.component_type = SurfaceParams::ComponentTypeFromRenderTarget(config.format);
1112 color_params.UpdateParams(); 1112 color_params.UpdateParams();
diff --git a/src/yuzu/debugger/graphics/graphics_surface.cpp b/src/yuzu/debugger/graphics/graphics_surface.cpp
index 5cadb807e..1fbca8ad0 100644
--- a/src/yuzu/debugger/graphics/graphics_surface.cpp
+++ b/src/yuzu/debugger/graphics/graphics_surface.cpp
@@ -378,10 +378,10 @@ void GraphicsSurfaceWidget::OnUpdate() {
378 // TODO: Implement a good way to visualize alpha components! 378 // TODO: Implement a good way to visualize alpha components!
379 379
380 QImage decoded_image(surface_width, surface_height, QImage::Format_ARGB32); 380 QImage decoded_image(surface_width, surface_height, QImage::Format_ARGB32);
381 VAddr address = gpu.memory_manager->GpuToCpuAddress(surface_address); 381 boost::optional<VAddr> address = gpu.memory_manager->GpuToCpuAddress(surface_address);
382 382
383 auto unswizzled_data = 383 auto unswizzled_data =
384 Tegra::Texture::UnswizzleTexture(address, surface_format, surface_width, surface_height); 384 Tegra::Texture::UnswizzleTexture(*address, surface_format, surface_width, surface_height);
385 385
386 auto texture_data = Tegra::Texture::DecodeTexture(unswizzled_data, surface_format, 386 auto texture_data = Tegra::Texture::DecodeTexture(unswizzled_data, surface_format,
387 surface_width, surface_height); 387 surface_width, surface_height);
@@ -437,9 +437,9 @@ void GraphicsSurfaceWidget::SaveSurface() {
437 pixmap->save(&file, "PNG"); 437 pixmap->save(&file, "PNG");
438 } else if (selectedFilter == bin_filter) { 438 } else if (selectedFilter == bin_filter) {
439 auto& gpu = Core::System::GetInstance().GPU(); 439 auto& gpu = Core::System::GetInstance().GPU();
440 VAddr address = gpu.memory_manager->GpuToCpuAddress(surface_address); 440 boost::optional<VAddr> address = gpu.memory_manager->GpuToCpuAddress(surface_address);
441 441
442 const u8* buffer = Memory::GetPointer(address); 442 const u8* buffer = Memory::GetPointer(*address);
443 ASSERT_MSG(buffer != nullptr, "Memory not accessible"); 443 ASSERT_MSG(buffer != nullptr, "Memory not accessible");
444 444
445 QFile file(filename); 445 QFile file(filename);