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| author | 2018-06-12 14:19:25 -0400 | |
|---|---|---|
| committer | 2018-06-12 14:19:25 -0400 | |
| commit | 2015a1b1804d56283a95753b10023d3fa277a854 (patch) | |
| tree | 0a82eb76ecce76d3b501a827033a0d283cbbbac7 /src | |
| parent | Merge pull request #557 from shinyquagsire23/libnx-hid-fix (diff) | |
| parent | GPU: Implemented the iadd32i shader instruction. (diff) | |
| download | yuzu-2015a1b1804d56283a95753b10023d3fa277a854.tar.gz yuzu-2015a1b1804d56283a95753b10023d3fa277a854.tar.xz yuzu-2015a1b1804d56283a95753b10023d3fa277a854.zip | |
Merge pull request #558 from Subv/iadd32i
GPU: Implemented the iadd32i shader instruction.
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 12 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 21 |
2 files changed, 31 insertions, 2 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index c158ffed2..29d88192e 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -216,7 +216,7 @@ union Instruction { | |||
| 216 | 216 | ||
| 217 | union { | 217 | union { |
| 218 | BitField<20, 19, u64> imm20_19; | 218 | BitField<20, 19, u64> imm20_19; |
| 219 | BitField<20, 32, u64> imm20_32; | 219 | BitField<20, 32, s64> imm20_32; |
| 220 | BitField<45, 1, u64> negate_b; | 220 | BitField<45, 1, u64> negate_b; |
| 221 | BitField<46, 1, u64> abs_a; | 221 | BitField<46, 1, u64> abs_a; |
| 222 | BitField<48, 1, u64> negate_a; | 222 | BitField<48, 1, u64> negate_a; |
| @@ -246,7 +246,7 @@ union Instruction { | |||
| 246 | 246 | ||
| 247 | float GetImm20_32() const { | 247 | float GetImm20_32() const { |
| 248 | float result{}; | 248 | float result{}; |
| 249 | u32 imm{static_cast<u32>(imm20_32)}; | 249 | s32 imm{static_cast<s32>(imm20_32)}; |
| 250 | std::memcpy(&result, &imm, sizeof(imm)); | 250 | std::memcpy(&result, &imm, sizeof(imm)); |
| 251 | return result; | 251 | return result; |
| 252 | } | 252 | } |
| @@ -270,6 +270,11 @@ union Instruction { | |||
| 270 | } alu_integer; | 270 | } alu_integer; |
| 271 | 271 | ||
| 272 | union { | 272 | union { |
| 273 | BitField<54, 1, u64> saturate; | ||
| 274 | BitField<56, 1, u64> negate_a; | ||
| 275 | } iadd32i; | ||
| 276 | |||
| 277 | union { | ||
| 273 | BitField<20, 8, u64> shift_position; | 278 | BitField<20, 8, u64> shift_position; |
| 274 | BitField<28, 8, u64> shift_length; | 279 | BitField<28, 8, u64> shift_length; |
| 275 | BitField<48, 1, u64> negate_b; | 280 | BitField<48, 1, u64> negate_b; |
| @@ -450,6 +455,7 @@ public: | |||
| 450 | IADD_C, | 455 | IADD_C, |
| 451 | IADD_R, | 456 | IADD_R, |
| 452 | IADD_IMM, | 457 | IADD_IMM, |
| 458 | IADD32I, | ||
| 453 | ISCADD_C, // Scale and Add | 459 | ISCADD_C, // Scale and Add |
| 454 | ISCADD_R, | 460 | ISCADD_R, |
| 455 | ISCADD_IMM, | 461 | ISCADD_IMM, |
| @@ -509,6 +515,7 @@ public: | |||
| 509 | Trivial, | 515 | Trivial, |
| 510 | Arithmetic, | 516 | Arithmetic, |
| 511 | ArithmeticInteger, | 517 | ArithmeticInteger, |
| 518 | ArithmeticIntegerImmediate, | ||
| 512 | Bfe, | 519 | Bfe, |
| 513 | Logic, | 520 | Logic, |
| 514 | Shift, | 521 | Shift, |
| @@ -641,6 +648,7 @@ private: | |||
| 641 | INST("0100110000010---", Id::IADD_C, Type::ArithmeticInteger, "IADD_C"), | 648 | INST("0100110000010---", Id::IADD_C, Type::ArithmeticInteger, "IADD_C"), |
| 642 | INST("0101110000010---", Id::IADD_R, Type::ArithmeticInteger, "IADD_R"), | 649 | INST("0101110000010---", Id::IADD_R, Type::ArithmeticInteger, "IADD_R"), |
| 643 | INST("0011100-00010---", Id::IADD_IMM, Type::ArithmeticInteger, "IADD_IMM"), | 650 | INST("0011100-00010---", Id::IADD_IMM, Type::ArithmeticInteger, "IADD_IMM"), |
| 651 | INST("0001110---------", Id::IADD32I, Type::ArithmeticIntegerImmediate, "IADD32I"), | ||
| 644 | INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"), | 652 | INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"), |
| 645 | INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"), | 653 | INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"), |
| 646 | INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"), | 654 | INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"), |
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index b94b79384..7ce150fda 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -1003,6 +1003,27 @@ private: | |||
| 1003 | break; | 1003 | break; |
| 1004 | } | 1004 | } |
| 1005 | 1005 | ||
| 1006 | case OpCode::Type::ArithmeticIntegerImmediate: { | ||
| 1007 | std::string op_a = regs.GetRegisterAsInteger(instr.gpr8); | ||
| 1008 | |||
| 1009 | if (instr.iadd32i.negate_a) | ||
| 1010 | op_a = '-' + op_a; | ||
| 1011 | |||
| 1012 | std::string op_b = '(' + std::to_string(instr.alu.imm20_32.Value()) + ')'; | ||
| 1013 | |||
| 1014 | switch (opcode->GetId()) { | ||
| 1015 | case OpCode::Id::IADD32I: | ||
| 1016 | regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1, | ||
| 1017 | instr.iadd32i.saturate != 0); | ||
| 1018 | break; | ||
| 1019 | default: { | ||
| 1020 | NGLOG_CRITICAL(HW_GPU, "Unhandled ArithmeticIntegerImmediate instruction: {}", | ||
| 1021 | opcode->GetName()); | ||
| 1022 | UNREACHABLE(); | ||
| 1023 | } | ||
| 1024 | } | ||
| 1025 | break; | ||
| 1026 | } | ||
| 1006 | case OpCode::Type::ArithmeticInteger: { | 1027 | case OpCode::Type::ArithmeticInteger: { |
| 1007 | std::string op_a = regs.GetRegisterAsInteger(instr.gpr8); | 1028 | std::string op_a = regs.GetRegisterAsInteger(instr.gpr8); |
| 1008 | 1029 | ||