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authorGravatar ReinUsesLisp2021-02-22 02:45:50 -0300
committerGravatar ameerj2021-07-22 21:51:22 -0400
commit18a766b3622baa40596490dbd4912f94e9980a76 (patch)
treede34dbbbd81f6f980308b165a812445b224bd8fb /src
parentspirv: Fixes and Intel specific workarounds (diff)
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shader: Fix MOV(reg), add SHL variants and emit neg and abs instructions
Diffstat (limited to 'src')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.h4
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp8
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_left.cpp8
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp2
4 files changed, 11 insertions, 11 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index cec80c13e..1b9be445e 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -181,8 +181,8 @@ void EmitIAdd64(EmitContext& ctx);
181Id EmitISub32(EmitContext& ctx, Id a, Id b); 181Id EmitISub32(EmitContext& ctx, Id a, Id b);
182void EmitISub64(EmitContext& ctx); 182void EmitISub64(EmitContext& ctx);
183Id EmitIMul32(EmitContext& ctx, Id a, Id b); 183Id EmitIMul32(EmitContext& ctx, Id a, Id b);
184void EmitINeg32(EmitContext& ctx); 184Id EmitINeg32(EmitContext& ctx, Id value);
185void EmitIAbs32(EmitContext& ctx); 185Id EmitIAbs32(EmitContext& ctx, Id value);
186Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift); 186Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
187void EmitShiftRightLogical32(EmitContext& ctx); 187void EmitShiftRightLogical32(EmitContext& ctx);
188void EmitShiftRightArithmetic32(EmitContext& ctx); 188void EmitShiftRightArithmetic32(EmitContext& ctx);
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 4c0b5990d..329dcb351 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -58,12 +58,12 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b) {
58 return ctx.OpIMul(ctx.U32[1], a, b); 58 return ctx.OpIMul(ctx.U32[1], a, b);
59} 59}
60 60
61void EmitINeg32(EmitContext&) { 61Id EmitINeg32(EmitContext& ctx, Id value) {
62 throw NotImplementedException("SPIR-V Instruction"); 62 return ctx.OpSNegate(ctx.U32[1], value);
63} 63}
64 64
65void EmitIAbs32(EmitContext&) { 65Id EmitIAbs32(EmitContext& ctx, Id value) {
66 throw NotImplementedException("SPIR-V Instruction"); 66 return ctx.OpSAbs(ctx.U32[1], value);
67} 67}
68 68
69Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) { 69Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_left.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_left.cpp
index b752785d4..d8a5158b5 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_left.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_left.cpp
@@ -56,12 +56,12 @@ void SHL(TranslatorVisitor& v, u64 insn, const IR::U32& unsafe_shift) {
56} 56}
57} // Anonymous namespace 57} // Anonymous namespace
58 58
59void TranslatorVisitor::SHL_reg(u64) { 59void TranslatorVisitor::SHL_reg(u64 insn) {
60 throw NotImplementedException("SHL_reg"); 60 SHL(*this, insn, GetReg20(insn));
61} 61}
62 62
63void TranslatorVisitor::SHL_cbuf(u64) { 63void TranslatorVisitor::SHL_cbuf(u64 insn) {
64 throw NotImplementedException("SHL_cbuf"); 64 SHL(*this, insn, GetCbuf(insn));
65} 65}
66 66
67void TranslatorVisitor::SHL_imm(u64 insn) { 67void TranslatorVisitor::SHL_imm(u64 insn) {
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
index c3c4b9abd..6bb08db8a 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
@@ -26,7 +26,7 @@ void MOV(TranslatorVisitor& v, u64 insn, const IR::U32& src, bool is_mov32i = fa
26} // Anonymous namespace 26} // Anonymous namespace
27 27
28void TranslatorVisitor::MOV_reg(u64 insn) { 28void TranslatorVisitor::MOV_reg(u64 insn) {
29 MOV(*this, insn, GetReg8(insn)); 29 MOV(*this, insn, GetReg20(insn));
30} 30}
31 31
32void TranslatorVisitor::MOV_cbuf(u64 insn) { 32void TranslatorVisitor::MOV_cbuf(u64 insn) {