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authorGravatar MerryMage2016-08-22 15:06:35 +0100
committerGravatar MerryMage2016-08-22 15:13:33 +0100
commit15b2eec4bdeadb6287a45c8d6fc77260280b45c8 (patch)
treea591c269b37df61ba81873e72ea45bccd8bc8d37 /src
parentcitra: Default to HW renderer. (diff)
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dyncom: Read-after-write in SMLA
In the case when RD === RN, RD was updated before AddOverflow was called to check for an overflow, resulting in an incorrect state of the Q flag.
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 6d5fb7aec..c8d45c6db 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -2820,10 +2820,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
2820 operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15); 2820 operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15);
2821 else 2821 else
2822 operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31); 2822 operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31);
2823 RD = operand1 * operand2 + RN;
2824 2823
2825 if (AddOverflow(operand1 * operand2, RN, RD)) 2824 u32 product = operand1 * operand2;
2825 u32 result = product + RN;
2826 if (AddOverflow(product, RN, result))
2826 cpu->Cpsr |= (1 << 27); 2827 cpu->Cpsr |= (1 << 27);
2828 RD = result;
2827 } 2829 }
2828 cpu->Reg[15] += cpu->GetInstructionSize(); 2830 cpu->Reg[15] += cpu->GetInstructionSize();
2829 INC_PC(sizeof(smla_inst)); 2831 INC_PC(sizeof(smla_inst));