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| author | 2018-12-21 17:25:49 -0300 | |
|---|---|---|
| committer | 2019-01-15 17:54:52 -0300 | |
| commit | 148a6418ede720681f464eca928c7c445f37db79 (patch) | |
| tree | d4f04564fb935a2e0e08d81e6a4e3a9fa51d4837 /src | |
| parent | video_core: Address feedback (diff) | |
| download | yuzu-148a6418ede720681f464eca928c7c445f37db79.tar.gz yuzu-148a6418ede720681f464eca928c7c445f37db79.tar.xz yuzu-148a6418ede720681f464eca928c7c445f37db79.zip | |
shader_decode: Implement FFMA
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/shader/decode/ffma.cpp | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/src/video_core/shader/decode/ffma.cpp b/src/video_core/shader/decode/ffma.cpp index 2044113f0..0adc85476 100644 --- a/src/video_core/shader/decode/ffma.cpp +++ b/src/video_core/shader/decode/ffma.cpp | |||
| @@ -16,7 +16,42 @@ u32 ShaderIR::DecodeFfma(BasicBlock& bb, u32 pc) { | |||
| 16 | const Instruction instr = {program_code[pc]}; | 16 | const Instruction instr = {program_code[pc]}; |
| 17 | const auto opcode = OpCode::Decode(instr); | 17 | const auto opcode = OpCode::Decode(instr); |
| 18 | 18 | ||
| 19 | UNIMPLEMENTED(); | 19 | UNIMPLEMENTED_IF_MSG(instr.ffma.cc != 0, "FFMA cc not implemented"); |
| 20 | UNIMPLEMENTED_IF_MSG(instr.ffma.tab5980_0 != 1, "FFMA tab5980_0({}) not implemented", | ||
| 21 | instr.ffma.tab5980_0.Value()); // Seems to be 1 by default based on SMO | ||
| 22 | UNIMPLEMENTED_IF_MSG(instr.ffma.tab5980_1 != 0, "FFMA tab5980_1({}) not implemented", | ||
| 23 | instr.ffma.tab5980_1.Value()); | ||
| 24 | UNIMPLEMENTED_IF_MSG(instr.generates_cc, | ||
| 25 | "Condition codes generation in FFMA is not implemented"); | ||
| 26 | |||
| 27 | const Node op_a = GetRegister(instr.gpr8); | ||
| 28 | |||
| 29 | auto [op_b, op_c] = [&]() -> std::tuple<Node, Node> { | ||
| 30 | switch (opcode->get().GetId()) { | ||
| 31 | case OpCode::Id::FFMA_CR: { | ||
| 32 | return {GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset), | ||
| 33 | GetRegister(instr.gpr39)}; | ||
| 34 | } | ||
| 35 | case OpCode::Id::FFMA_RR: | ||
| 36 | return {GetRegister(instr.gpr20), GetRegister(instr.gpr39)}; | ||
| 37 | case OpCode::Id::FFMA_RC: { | ||
| 38 | return {GetRegister(instr.gpr39), | ||
| 39 | GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset)}; | ||
| 40 | } | ||
| 41 | case OpCode::Id::FFMA_IMM: | ||
| 42 | return {GetImmediate19(instr), GetRegister(instr.gpr39)}; | ||
| 43 | default: | ||
| 44 | UNIMPLEMENTED_MSG("Unhandled FFMA instruction: {}", opcode->get().GetName()); | ||
| 45 | } | ||
| 46 | }(); | ||
| 47 | |||
| 48 | op_b = GetOperandAbsNegFloat(op_b, false, instr.ffma.negate_b); | ||
| 49 | op_c = GetOperandAbsNegFloat(op_c, false, instr.ffma.negate_c); | ||
| 50 | |||
| 51 | Node value = Operation(OperationCode::FFma, PRECISE, op_a, op_b, op_c); | ||
| 52 | value = GetSaturatedFloat(value, instr.alu.saturate_d); | ||
| 53 | |||
| 54 | SetRegister(bb, instr.gpr0, value); | ||
| 20 | 55 | ||
| 21 | return pc; | 56 | return pc; |
| 22 | } | 57 | } |