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authorGravatar bunnei2014-05-16 20:52:46 -0400
committerGravatar bunnei2014-05-16 20:52:46 -0400
commit145a91f21fae23b258b91cc0f841fda16129504a (patch)
tree2af6b30c5820291a81709a12c65b9a7cd8267e40 /src
parent- removed unused stubbed out code (diff)
downloadyuzu-145a91f21fae23b258b91cc0f841fda16129504a.tar.gz
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- reenabled MCR and MRC functions now that VFP is attached
- removed HLE::CallMCR function (was pointless)
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/interpreter/armemu.h31
-rw-r--r--src/core/arm/interpreter/armsupp.cpp156
-rw-r--r--src/core/hle/coprocessor.cpp20
-rw-r--r--src/core/hle/coprocessor.h3
4 files changed, 94 insertions, 116 deletions
diff --git a/src/core/arm/interpreter/armemu.h b/src/core/arm/interpreter/armemu.h
index ad4057465..7ccb07e8d 100644
--- a/src/core/arm/interpreter/armemu.h
+++ b/src/core/arm/interpreter/armemu.h
@@ -17,9 +17,9 @@
17#ifndef __ARMEMU_H__ 17#ifndef __ARMEMU_H__
18#define __ARMEMU_H__ 18#define __ARMEMU_H__
19 19
20#include "common/common.h" 20
21#include "armdefs.h" 21#include "core/arm/interpreter/skyeye_defs.h"
22//#include "skyeye.h" 22#include "core/arm/interpreter/armdefs.h"
23 23
24extern ARMword isize; 24extern ARMword isize;
25 25
@@ -73,9 +73,7 @@ extern ARMword isize;
73#define ASSIGNT(res) state->TFlag = res 73#define ASSIGNT(res) state->TFlag = res
74#define INSN_SIZE (TFLAG ? 2 : 4) 74#define INSN_SIZE (TFLAG ? 2 : 4)
75#else 75#else
76#define TBIT (1L << 5)
77#define INSN_SIZE 4 76#define INSN_SIZE 4
78#define TFLAG 0
79#endif 77#endif
80 78
81/*add armv6 CPSR feature*/ 79/*add armv6 CPSR feature*/
@@ -166,6 +164,7 @@ extern ARMword isize;
166#define PCWRAP(pc) ((pc) & R15PCBITS) 164#define PCWRAP(pc) ((pc) & R15PCBITS)
167#endif 165#endif
168 166
167#define PC (state->Reg[15] & PCMASK)
169#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS)) 168#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
170#define R15INT (state->Reg[15] & R15INTBITS) 169#define R15INT (state->Reg[15] & R15INTBITS)
171#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS)) 170#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
@@ -180,11 +179,11 @@ extern ARMword isize;
180#define ER15INT (IFFLAGS << 26) 179#define ER15INT (IFFLAGS << 26)
181#define EMODE (state->Mode) 180#define EMODE (state->Mode)
182 181
183//#ifdef MODET 182#ifdef MODET
184//#define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) 183#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
185//#else 184#else
186//#define CPSR (ECC | EINT | EMODE) 185#define CPSR (ECC | EINT | EMODE)
187//#endif 186#endif
188 187
189#ifdef MODE32 188#ifdef MODE32
190#define PATCHR15 189#define PATCHR15
@@ -240,12 +239,12 @@ extern ARMword isize;
240 } \ 239 } \
241 while (0) 240 while (0)
242 241
243//#ifndef MODE32 242#ifndef MODE32
244#define VECTORS 0x20 243#define VECTORS 0x20
245#define LEGALADDR 0x03ffffff 244#define LEGALADDR 0x03ffffff
246#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig) 245#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
247#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig) 246#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
248//#endif 247#endif
249 248
250#define INTERNALABORT(address) \ 249#define INTERNALABORT(address) \
251 do \ 250 do \
@@ -421,9 +420,9 @@ extern ARMword isize;
421 || (read_cp15_reg (15, 0, 1) & (1 << (CP)))) 420 || (read_cp15_reg (15, 0, 1) & (1 << (CP))))
422*/ 421*/
423#define CP_ACCESS_ALLOWED(STATE, CP) \ 422#define CP_ACCESS_ALLOWED(STATE, CP) \
424 (((CP) >= 14) \ 423 ( ((CP) >= 14) \
425 || (!(STATE)->is_XScale) \ 424 || (! (STATE)->is_XScale) \
426 || (xscale_cp15_cp_access_allowed(STATE, 15, CP))) 425 || (xscale_cp15_cp_access_allowed(STATE,15,CP)))
427 426
428/* Macro to rotate n right by b bits. */ 427/* Macro to rotate n right by b bits. */
429#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b)))) 428#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))
@@ -515,7 +514,7 @@ tdstate;
515 * out-of-updated with the newer ISA. 514 * out-of-updated with the newer ISA.
516 * -- Michael.Kang 515 * -- Michael.Kang
517 ********************************************************************************/ 516 ********************************************************************************/
518#define UNDEF_WARNING ERROR_LOG(ARM11, "undefined or unpredicted behavior for arm instruction.\n"); 517#define UNDEF_WARNING WARN_LOG(ARM11, "undefined or unpredicted behavior for arm instruction.\n");
519 518
520/* Macros to scrutinize instructions. */ 519/* Macros to scrutinize instructions. */
521#define UNDEF_Test UNDEF_WARNING 520#define UNDEF_Test UNDEF_WARNING
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index e531dceda..7816c4c42 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -15,11 +15,9 @@
15 along with this program; if not, write to the Free Software 15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17 17
18#include "armdefs.h" 18#include "core/arm/interpreter/armdefs.h"
19#include "armemu.h" 19#include "core/arm/interpreter/armemu.h"
20 20#include "core/arm/interpreter/skyeye_defs.h"
21//#include "ansidecl.h"
22#include "skyeye_defs.h"
23#include "core/hle/coprocessor.h" 21#include "core/hle/coprocessor.h"
24#include "core/arm/disassembler/arm_disasm.h" 22#include "core/arm/disassembler/arm_disasm.h"
25 23
@@ -127,8 +125,7 @@ ARMul_GetCPSR (ARMul_State * state)
127{ 125{
128 //chy 2003-08-20: below is from gdb20030716, maybe isn't suitable for system simulator 126 //chy 2003-08-20: below is from gdb20030716, maybe isn't suitable for system simulator
129 //return (CPSR | state->Cpsr); for gdb20030716 127 //return (CPSR | state->Cpsr); for gdb20030716
130 // NOTE(bunnei): Changed this from [now] commented out macro "CPSR" 128 return (CPSR); //had be tested in old skyeye with gdb5.0-5.3
131 return ((ECC | EINT | EMODE | (TFLAG << 5))); //had be tested in old skyeye with gdb5.0-5.3
132} 129}
133 130
134/* This routine sets the value of the CPSR. */ 131/* This routine sets the value of the CPSR. */
@@ -145,7 +142,7 @@ ARMul_SetCPSR (ARMul_State * state, ARMword value)
145 142
146void 143void
147ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs) 144ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
148{ 145{
149 state->Cpsr = ARMul_GetCPSR (state); 146 state->Cpsr = ARMul_GetCPSR (state);
150 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode 147 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
151 if (state->Mode != USER26MODE && state->Mode != USER32MODE ) { 148 if (state->Mode != USER26MODE && state->Mode != USER32MODE ) {
@@ -500,8 +497,8 @@ ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address)
500 return; 497 return;
501 } 498 }
502 499
503 if (ADDREXCEPT (address)) 500 //if (ADDREXCEPT (address))
504 INTERNALABORT (address); 501 // INTERNALABORT (address);
505 502
506 cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0); 503 cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0);
507 while (cpab == ARMul_BUSY) { 504 while (cpab == ARMul_BUSY) {
@@ -594,8 +591,8 @@ ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
594 return; 591 return;
595 } 592 }
596 593
597 if (ADDREXCEPT (address) || VECTORACCESS (address)) 594 //if (ADDREXCEPT (address) || VECTORACCESS (address))
598 INTERNALABORT (address); 595 // INTERNALABORT (address);
599 596
600 cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data); 597 cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data);
601 while (cpab == ARMul_BUSY) { 598 while (cpab == ARMul_BUSY) {
@@ -661,40 +658,39 @@ ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
661void 658void
662ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source) 659ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source)
663{ 660{
664 HLE::CallMCR(instr, source); 661 unsigned cpab;
665 //unsigned cpab; 662
666 663 //printf("SKYEYE ARMul_MCR, CPnum is %x, source %x\n",CPNum, source);
667 ////printf("SKYEYE ARMul_MCR, CPnum is %x, source %x\n",CPNum, source); 664 if (!CP_ACCESS_ALLOWED (state, CPNum)) {
668 //if (!CP_ACCESS_ALLOWED (state, CPNum)) { 665 //chy 2004-07-19 should fix in the future ????!!!!
669 // //chy 2004-07-19 should fix in the future ????!!!! 666 //printf("SKYEYE ARMul_MCR, ACCESS_not ALLOWed, UndefinedInstr CPnum is %x, source %x\n",CPNum, source);
670 // //printf("SKYEYE ARMul_MCR, ACCESS_not ALLOWed, UndefinedInstr CPnum is %x, source %x\n",CPNum, source); 667 ARMul_UndefInstr (state, instr);
671 // ARMul_UndefInstr (state, instr); 668 return;
672 // return; 669 }
673 //} 670
674 671 cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source);
675 //cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source); 672
676 673 while (cpab == ARMul_BUSY) {
677 //while (cpab == ARMul_BUSY) { 674 ARMul_Icycles (state, 1, 0);
678 // ARMul_Icycles (state, 1, 0); 675
679 676 if (IntPending (state)) {
680 // if (IntPending (state)) { 677 cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT,
681 // cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, 678 instr, 0);
682 // instr, 0); 679 return;
683 // return; 680 }
684 // } 681 else
685 // else 682 cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr,
686 // cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, 683 source);
687 // source); 684 }
688 //} 685
689 686 if (cpab == ARMul_CANT) {
690 //if (cpab == ARMul_CANT) { 687 printf ("SKYEYE ARMul_MCR, CANT, UndefinedInstr %x CPnum is %x, source %x\n", instr, CPNum, source);
691 // printf ("SKYEYE ARMul_MCR, CANT, UndefinedInstr %x CPnum is %x, source %x\n", instr, CPNum, source); 688 ARMul_Abort (state, ARMul_UndefinedInstrV);
692 // ARMul_Abort (state, ARMul_UndefinedInstrV); 689 }
693 //} 690 else {
694 //else { 691 BUSUSEDINCPCN;
695 // BUSUSEDINCPCN; 692 ARMul_Ccycles (state, 1, 0);
696 // ARMul_Ccycles (state, 1, 0); 693 }
697 //}
698} 694}
699 695
700/* This function does the Busy-Waiting for an MCRR instruction. */ 696/* This function does the Busy-Waiting for an MCRR instruction. */
@@ -742,37 +738,41 @@ ARMul_MRC (ARMul_State * state, ARMword instr)
742 738
743 ARMword result = HLE::CallMRC(instr); 739 ARMword result = HLE::CallMRC(instr);
744 740
745 ////printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr); 741 if (result != -1) {
746 //if (!CP_ACCESS_ALLOWED (state, CPNum)) { 742 return result;
747 // //chy 2004-07-19 should fix in the future????!!!! 743 }
748 // //printf("SKYEYE ARMul_MRC,NOT ALLOWed UndefInstr CPnum is %x, instr %x\n",CPNum, instr); 744
749 // ARMul_UndefInstr (state, instr); 745 //printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr);
750 // return -1; 746 if (!CP_ACCESS_ALLOWED (state, CPNum)) {
751 //} 747 //chy 2004-07-19 should fix in the future????!!!!
752 748 //printf("SKYEYE ARMul_MRC,NOT ALLOWed UndefInstr CPnum is %x, instr %x\n",CPNum, instr);
753 //cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result); 749 ARMul_UndefInstr (state, instr);
754 //while (cpab == ARMul_BUSY) { 750 return -1;
755 // ARMul_Icycles (state, 1, 0); 751 }
756 // if (IntPending (state)) { 752
757 // cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, 753 cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result);
758 // instr, 0); 754 while (cpab == ARMul_BUSY) {
759 // return (0); 755 ARMul_Icycles (state, 1, 0);
760 // } 756 if (IntPending (state)) {
761 // else 757 cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT,
762 // cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, 758 instr, 0);
763 // &result); 759 return (0);
764 //} 760 }
765 //if (cpab == ARMul_CANT) { 761 else
766 // printf ("SKYEYE ARMul_MRC,CANT UndefInstr CPnum is %x, instr %x\n", CPNum, instr); 762 cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr,
767 // ARMul_Abort (state, ARMul_UndefinedInstrV); 763 &result);
768 // /* Parent will destroy the flags otherwise. */ 764 }
769 // result = ECC; 765 if (cpab == ARMul_CANT) {
770 //} 766 printf ("SKYEYE ARMul_MRC,CANT UndefInstr CPnum is %x, instr %x\n", CPNum, instr);
771 //else { 767 ARMul_Abort (state, ARMul_UndefinedInstrV);
772 // BUSUSEDINCPCN; 768 /* Parent will destroy the flags otherwise. */
773 // ARMul_Ccycles (state, 1, 0); 769 result = ECC;
774 // ARMul_Icycles (state, 1, 0); 770 }
775 //} 771 else {
772 BUSUSEDINCPCN;
773 ARMul_Ccycles (state, 1, 0);
774 ARMul_Icycles (state, 1, 0);
775 }
776 776
777 return result; 777 return result;
778} 778}
@@ -907,9 +907,7 @@ ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay,
907 state->Now = ARMul_Time (state); 907 state->Now = ARMul_Time (state);
908 when = (state->Now + delay) % EVENTLISTSIZE; 908 when = (state->Now + delay) % EVENTLISTSIZE;
909 event = (struct EventNode *) malloc (sizeof (struct EventNode)); 909 event = (struct EventNode *) malloc (sizeof (struct EventNode));
910
911 _dbg_assert_msg_(ARM11, event, "SKYEYE:ARMul_ScheduleEvent: malloc event error\n"); 910 _dbg_assert_msg_(ARM11, event, "SKYEYE:ARMul_ScheduleEvent: malloc event error\n");
912
913 event->func = what; 911 event->func = what;
914 event->next = *(state->EventPtr + when); 912 event->next = *(state->EventPtr + when);
915 *(state->EventPtr + when) = event; 913 *(state->EventPtr + when) = event;
diff --git a/src/core/hle/coprocessor.cpp b/src/core/hle/coprocessor.cpp
index 74305331c..39674ee64 100644
--- a/src/core/hle/coprocessor.cpp
+++ b/src/core/hle/coprocessor.cpp
@@ -9,42 +9,26 @@
9 9
10namespace HLE { 10namespace HLE {
11 11
12/// Data synchronization barrier
13u32 DataSynchronizationBarrier() {
14 return 0;
15}
16
17/// Returns the coprocessor (in this case, syscore) command buffer pointer 12/// Returns the coprocessor (in this case, syscore) command buffer pointer
18Addr GetThreadCommandBuffer() { 13Addr GetThreadCommandBuffer() {
19 // Called on insruction: mrc p15, 0, r0, c13, c0, 3 14 // Called on insruction: mrc p15, 0, r0, c13, c0, 3
20 return Memory::KERNEL_MEMORY_VADDR; 15 return Memory::KERNEL_MEMORY_VADDR;
21} 16}
22 17
23/// Call an MCR (move to coprocessor from ARM register) instruction in HLE
24s32 CallMCR(u32 instruction, u32 value) {
25 CoprocessorOperation operation = (CoprocessorOperation)((instruction >> 20) & 0xFF);
26 ERROR_LOG(OSHLE, "unimplemented MCR instruction=0x%08X, operation=%02X, value=%08X",
27 instruction, operation, value);
28 return 0;
29}
30
31/// Call an MRC (move to ARM register from coprocessor) instruction in HLE 18/// Call an MRC (move to ARM register from coprocessor) instruction in HLE
32s32 CallMRC(u32 instruction) { 19s32 CallMRC(u32 instruction) {
33 CoprocessorOperation operation = (CoprocessorOperation)((instruction >> 20) & 0xFF); 20 CoprocessorOperation operation = (CoprocessorOperation)((instruction >> 20) & 0xFF);
34 21
35 switch (operation) { 22 switch (operation) {
36 23
37 case DATA_SYNCHRONIZATION_BARRIER:
38 return DataSynchronizationBarrier();
39
40 case CALL_GET_THREAD_COMMAND_BUFFER: 24 case CALL_GET_THREAD_COMMAND_BUFFER:
41 return GetThreadCommandBuffer(); 25 return GetThreadCommandBuffer();
42 26
43 default: 27 default:
44 ERROR_LOG(OSHLE, "unimplemented MRC instruction 0x%08X", instruction); 28 //DEBUG_LOG(OSHLE, "unknown MRC call 0x%08X", instruction);
45 break; 29 break;
46 } 30 }
47 return 0; 31 return -1;
48} 32}
49 33
50} // namespace 34} // namespace
diff --git a/src/core/hle/coprocessor.h b/src/core/hle/coprocessor.h
index 03822af13..b08d6f3ee 100644
--- a/src/core/hle/coprocessor.h
+++ b/src/core/hle/coprocessor.h
@@ -14,9 +14,6 @@ enum CoprocessorOperation {
14 CALL_GET_THREAD_COMMAND_BUFFER = 0xE1, 14 CALL_GET_THREAD_COMMAND_BUFFER = 0xE1,
15}; 15};
16 16
17/// Call an MCR (move to coprocessor from ARM register) instruction in HLE
18s32 CallMCR(u32 instruction, u32 value);
19
20/// Call an MRC (move to ARM register from coprocessor) instruction in HLE 17/// Call an MRC (move to ARM register from coprocessor) instruction in HLE
21s32 CallMRC(u32 instruction); 18s32 CallMRC(u32 instruction);
22 19