summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorGravatar bunnei2018-10-22 12:53:47 -0400
committerGravatar GitHub2018-10-22 12:53:47 -0400
commit1226a5706e3e877092d2d2a4d014fd548d81a01b (patch)
treef742d23aaf0f7b6fa2201c8efc3312dbe193a54b /src
parentMerge pull request #1546 from lioncash/svc-again (diff)
parentFixed FSETP and FSET (diff)
downloadyuzu-1226a5706e3e877092d2d2a4d014fd548d81a01b.tar.gz
yuzu-1226a5706e3e877092d2d2a4d014fd548d81a01b.tar.xz
yuzu-1226a5706e3e877092d2d2a4d014fd548d81a01b.zip
Merge pull request #1547 from FernandoS27/fix-fset
Fixed FSETP and FSET
Diffstat (limited to 'src')
-rw-r--r--src/video_core/engines/shader_bytecode.h2
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp40
2 files changed, 12 insertions, 30 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index e3d67ff87..67501cf0a 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -753,7 +753,6 @@ union Instruction {
753 BitField<45, 2, PredOperation> op; 753 BitField<45, 2, PredOperation> op;
754 BitField<47, 1, u64> ftz; 754 BitField<47, 1, u64> ftz;
755 BitField<48, 4, PredCondition> cond; 755 BitField<48, 4, PredCondition> cond;
756 BitField<56, 1, u64> neg_b;
757 } fsetp; 756 } fsetp;
758 757
759 union { 758 union {
@@ -828,7 +827,6 @@ union Instruction {
828 BitField<53, 1, u64> neg_b; 827 BitField<53, 1, u64> neg_b;
829 BitField<54, 1, u64> abs_a; 828 BitField<54, 1, u64> abs_a;
830 BitField<55, 1, u64> ftz; 829 BitField<55, 1, u64> ftz;
831 BitField<56, 1, u64> neg_imm;
832 } fset; 830 } fset;
833 831
834 union { 832 union {
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index a427353e9..b0eb879cc 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -2736,20 +2736,13 @@ private:
2736 break; 2736 break;
2737 } 2737 }
2738 case OpCode::Type::FloatSetPredicate: { 2738 case OpCode::Type::FloatSetPredicate: {
2739 std::string op_a = instr.fsetp.neg_a ? "-" : ""; 2739 const std::string op_a =
2740 op_a += regs.GetRegisterAsFloat(instr.gpr8); 2740 GetOperandAbsNeg(regs.GetRegisterAsFloat(instr.gpr8), instr.fsetp.abs_a != 0,
2741 2741 instr.fsetp.neg_a != 0);
2742 if (instr.fsetp.abs_a) {
2743 op_a = "abs(" + op_a + ')';
2744 }
2745 2742
2746 std::string op_b{}; 2743 std::string op_b;
2747 2744
2748 if (instr.is_b_imm) { 2745 if (instr.is_b_imm) {
2749 if (instr.fsetp.neg_b) {
2750 // Only the immediate version of fsetp has a neg_b bit.
2751 op_b += '-';
2752 }
2753 op_b += '(' + GetImmediate19(instr) + ')'; 2746 op_b += '(' + GetImmediate19(instr) + ')';
2754 } else { 2747 } else {
2755 if (instr.is_b_gpr) { 2748 if (instr.is_b_gpr) {
@@ -2945,33 +2938,24 @@ private:
2945 break; 2938 break;
2946 } 2939 }
2947 case OpCode::Type::FloatSet: { 2940 case OpCode::Type::FloatSet: {
2948 std::string op_a = instr.fset.neg_a ? "-" : ""; 2941 const std::string op_a = GetOperandAbsNeg(regs.GetRegisterAsFloat(instr.gpr8),
2949 op_a += regs.GetRegisterAsFloat(instr.gpr8); 2942 instr.fset.abs_a != 0, instr.fset.neg_a != 0);
2950
2951 if (instr.fset.abs_a) {
2952 op_a = "abs(" + op_a + ')';
2953 }
2954 2943
2955 std::string op_b = instr.fset.neg_b ? "-" : ""; 2944 std::string op_b;
2956 2945
2957 if (instr.is_b_imm) { 2946 if (instr.is_b_imm) {
2958 const std::string imm = GetImmediate19(instr); 2947 const std::string imm = GetImmediate19(instr);
2959 if (instr.fset.neg_imm) 2948 op_b = imm;
2960 op_b += "(-" + imm + ')';
2961 else
2962 op_b += imm;
2963 } else { 2949 } else {
2964 if (instr.is_b_gpr) { 2950 if (instr.is_b_gpr) {
2965 op_b += regs.GetRegisterAsFloat(instr.gpr20); 2951 op_b = regs.GetRegisterAsFloat(instr.gpr20);
2966 } else { 2952 } else {
2967 op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset, 2953 op_b = regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
2968 GLSLRegister::Type::Float); 2954 GLSLRegister::Type::Float);
2969 } 2955 }
2970 } 2956 }
2971 2957
2972 if (instr.fset.abs_b) { 2958 op_b = GetOperandAbsNeg(op_b, instr.fset.abs_b != 0, instr.fset.neg_b != 0);
2973 op_b = "abs(" + op_b + ')';
2974 }
2975 2959
2976 // The fset instruction sets a register to 1.0 or -1 (depending on the bf bit) if the 2960 // The fset instruction sets a register to 1.0 or -1 (depending on the bf bit) if the
2977 // condition is true, and to 0 otherwise. 2961 // condition is true, and to 0 otherwise.