diff options
| author | 2019-06-14 16:40:04 -0400 | |
|---|---|---|
| committer | 2019-06-20 21:38:34 -0300 | |
| commit | 082740d34db0996a0af73d7680c57e1abb31c712 (patch) | |
| tree | bcc9ecb6af93114eaf008f8a576b1a99b9f189fe /src | |
| parent | texture_cache: Initialize all siblings to invalid pixel format. (diff) | |
| download | yuzu-082740d34db0996a0af73d7680c57e1abb31c712.tar.gz yuzu-082740d34db0996a0af73d7680c57e1abb31c712.tar.xz yuzu-082740d34db0996a0af73d7680c57e1abb31c712.zip | |
surface: Correct format S8Z24
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/maxwell_dma.cpp | 2 | ||||
| -rw-r--r-- | src/video_core/surface.cpp | 4 | ||||
| -rw-r--r-- | src/video_core/texture_cache/texture_cache.h | 4 | ||||
| -rw-r--r-- | src/video_core/textures/texture.h | 4 |
4 files changed, 5 insertions, 9 deletions
diff --git a/src/video_core/engines/maxwell_dma.cpp b/src/video_core/engines/maxwell_dma.cpp index 3a5dfef0c..afb9578d0 100644 --- a/src/video_core/engines/maxwell_dma.cpp +++ b/src/video_core/engines/maxwell_dma.cpp | |||
| @@ -111,7 +111,7 @@ void MaxwellDMA::HandleCopy() { | |||
| 111 | 111 | ||
| 112 | memory_manager.WriteBlock(dest, write_buffer.data(), dst_size); | 112 | memory_manager.WriteBlock(dest, write_buffer.data(), dst_size); |
| 113 | } else { | 113 | } else { |
| 114 | ASSERT(regs.dst_params.BlockDepth() == 1); | 114 | ASSERT(regs.dst_params.BlockDepth() == 0); |
| 115 | 115 | ||
| 116 | const u32 src_bytes_per_pixel = regs.src_pitch / regs.x_count; | 116 | const u32 src_bytes_per_pixel = regs.src_pitch / regs.x_count; |
| 117 | 117 | ||
diff --git a/src/video_core/surface.cpp b/src/video_core/surface.cpp index 52a79e4a7..c50f6354d 100644 --- a/src/video_core/surface.cpp +++ b/src/video_core/surface.cpp | |||
| @@ -308,8 +308,8 @@ PixelFormat PixelFormatFromTextureFormat(Tegra::Texture::TextureFormat format, | |||
| 308 | return PixelFormat::Z32F; | 308 | return PixelFormat::Z32F; |
| 309 | case Tegra::Texture::TextureFormat::Z16: | 309 | case Tegra::Texture::TextureFormat::Z16: |
| 310 | return PixelFormat::Z16; | 310 | return PixelFormat::Z16; |
| 311 | case Tegra::Texture::TextureFormat::Z24S8: | 311 | case Tegra::Texture::TextureFormat::S8Z24: |
| 312 | return PixelFormat::Z24S8; | 312 | return PixelFormat::S8Z24; |
| 313 | case Tegra::Texture::TextureFormat::ZF32_X24S8: | 313 | case Tegra::Texture::TextureFormat::ZF32_X24S8: |
| 314 | return PixelFormat::Z32FS8; | 314 | return PixelFormat::Z32FS8; |
| 315 | case Tegra::Texture::TextureFormat::DXT1: | 315 | case Tegra::Texture::TextureFormat::DXT1: |
diff --git a/src/video_core/texture_cache/texture_cache.h b/src/video_core/texture_cache/texture_cache.h index 8213f434d..a9e61cba1 100644 --- a/src/video_core/texture_cache/texture_cache.h +++ b/src/video_core/texture_cache/texture_cache.h | |||
| @@ -534,10 +534,6 @@ private: | |||
| 534 | const auto host_ptr{memory_manager->GetPointer(gpu_addr)}; | 534 | const auto host_ptr{memory_manager->GetPointer(gpu_addr)}; |
| 535 | const auto cache_addr{ToCacheAddr(host_ptr)}; | 535 | const auto cache_addr{ToCacheAddr(host_ptr)}; |
| 536 | 536 | ||
| 537 | if (gpu_addr == 0x00000001682F0000ULL) { | ||
| 538 | LOG_CRITICAL(HW_GPU, "Here's the texture!"); | ||
| 539 | } | ||
| 540 | |||
| 541 | // Step 0: guarantee a valid surface | 537 | // Step 0: guarantee a valid surface |
| 542 | if (!cache_addr) { | 538 | if (!cache_addr) { |
| 543 | // Return a null surface if it's invalid | 539 | // Return a null surface if it's invalid |
diff --git a/src/video_core/textures/texture.h b/src/video_core/textures/texture.h index ddeed73d0..e3be018b9 100644 --- a/src/video_core/textures/texture.h +++ b/src/video_core/textures/texture.h | |||
| @@ -52,9 +52,9 @@ enum class TextureFormat : u32 { | |||
| 52 | DXT45 = 0x26, | 52 | DXT45 = 0x26, |
| 53 | DXN1 = 0x27, | 53 | DXN1 = 0x27, |
| 54 | DXN2 = 0x28, | 54 | DXN2 = 0x28, |
| 55 | Z24S8 = 0x29, | 55 | S8Z24 = 0x29, |
| 56 | X8Z24 = 0x2a, | 56 | X8Z24 = 0x2a, |
| 57 | S8Z24 = 0x2b, | 57 | Z24S8 = 0x2b, |
| 58 | X4V4Z24__COV4R4V = 0x2c, | 58 | X4V4Z24__COV4R4V = 0x2c, |
| 59 | X4V4Z24__COV8R8V = 0x2d, | 59 | X4V4Z24__COV8R8V = 0x2d, |
| 60 | V8Z24__COV4R12V = 0x2e, | 60 | V8Z24__COV4R12V = 0x2e, |