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| author |  ReinUsesLisp | 2018-12-20 23:57:09 -0300 |
|---|---|---|
| committer | ReinUsesLisp | 2019-01-15 17:54:50 -0300 |
| commit | 06cb910c6d9b0be664db4305f90974198f84ae98 (patch) | |
| tree | b1e194f9b560bdbb97d2334363ddf63dfd336e49 /src | |
| parent | shader_decode: Implement FMNMX_C, FMNMX_R and FMNMX_IMM (diff) | |
| download | yuzu-06cb910c6d9b0be664db4305f90974198f84ae98.tar.gz yuzu-06cb910c6d9b0be664db4305f90974198f84ae98.tar.xz yuzu-06cb910c6d9b0be664db4305f90974198f84ae98.zip | |
shader_decode: Stub RRO_C, RRO_R and RRO_IMM
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/shader/decode/arithmetic.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic.cpp b/src/video_core/shader/decode/arithmetic.cpp index 0b6654397..9f8c27b3e 100644 --- a/src/video_core/shader/decode/arithmetic.cpp +++ b/src/video_core/shader/decode/arithmetic.cpp | |||
| @@ -140,6 +140,15 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) { | |||
| 140 | Operation(OperationCode::Select, NO_PRECISE, condition, min, max)); | 140 | Operation(OperationCode::Select, NO_PRECISE, condition, min, max)); |
| 141 | break; | 141 | break; |
| 142 | } | 142 | } |
| 143 | case OpCode::Id::RRO_C: | ||
| 144 | case OpCode::Id::RRO_R: | ||
| 145 | case OpCode::Id::RRO_IMM: { | ||
| 146 | // Currently RRO is only implemented as a register move. | ||
| 147 | op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b); | ||
| 148 | SetRegister(bb, instr.gpr0, op_b); | ||
| 149 | LOG_WARNING(HW_GPU, "RRO instruction is incomplete"); | ||
| 150 | break; | ||
| 151 | } | ||
| 143 | default: | 152 | default: |
| 144 | UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName()); | 153 | UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName()); |
| 145 | } | 154 | } |