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authorGravatar Lioncash2015-05-14 11:58:05 -0400
committerGravatar Lioncash2015-05-14 14:32:07 -0400
commit0530fd249911a807bcaca2563d95d1f33298ad62 (patch)
tree873c9b412a66a64ac1b1dda5426abd2bded8e3b9 /src
parentdyncom: Remove unnecessary typedefs (diff)
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dyncom: Make translation-unit functions and variables static
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp130
1 files changed, 64 insertions, 66 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index ebc1b96b9..81d8c7026 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -68,6 +68,67 @@ static void remove_exclusive(ARMul_State* state, ARMword addr){
68 state->exclusive_tag = 0xFFFFFFFF; 68 state->exclusive_tag = 0xFFFFFFFF;
69} 69}
70 70
71static int CondPassed(ARMul_State* cpu, unsigned int cond) {
72 #define NFLAG cpu->NFlag
73 #define ZFLAG cpu->ZFlag
74 #define CFLAG cpu->CFlag
75 #define VFLAG cpu->VFlag
76
77 int temp = 0;
78
79 switch (cond) {
80 case 0x0:
81 temp = ZFLAG;
82 break;
83 case 0x1: // NE
84 temp = !ZFLAG;
85 break;
86 case 0x2: // CS
87 temp = CFLAG;
88 break;
89 case 0x3: // CC
90 temp = !CFLAG;
91 break;
92 case 0x4: // MI
93 temp = NFLAG;
94 break;
95 case 0x5: // PL
96 temp = !NFLAG;
97 break;
98 case 0x6: // VS
99 temp = VFLAG;
100 break;
101 case 0x7: // VC
102 temp = !VFLAG;
103 break;
104 case 0x8: // HI
105 temp = (CFLAG && !ZFLAG);
106 break;
107 case 0x9: // LS
108 temp = (!CFLAG || ZFLAG);
109 break;
110 case 0xa: // GE
111 temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
112 break;
113 case 0xb: // LT
114 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
115 break;
116 case 0xc: // GT
117 temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG));
118 break;
119 case 0xd: // LE
120 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
121 break;
122 case 0xe: // AL
123 temp = 1;
124 break;
125 case 0xf:
126 temp = 1;
127 break;
128 }
129 return temp;
130}
131
71static unsigned int DPO(Immediate)(ARMul_State* cpu, unsigned int sht_oper) { 132static unsigned int DPO(Immediate)(ARMul_State* cpu, unsigned int sht_oper) {
72 unsigned int immed_8 = BITS(sht_oper, 0, 7); 133 unsigned int immed_8 = BITS(sht_oper, 0, 7);
73 unsigned int rotate_imm = BITS(sht_oper, 8, 11); 134 unsigned int rotate_imm = BITS(sht_oper, 8, 11);
@@ -230,8 +291,6 @@ struct ldst_inst {
230}; 291};
231#define DEBUG_MSG LOG_DEBUG(Core_ARM11, "inst is %x", inst); CITRA_IGNORE_EXIT(0) 292#define DEBUG_MSG LOG_DEBUG(Core_ARM11, "inst is %x", inst); CITRA_IGNORE_EXIT(0)
232 293
233int CondPassed(ARMul_State* cpu, unsigned int cond);
234
235#define LnSWoUB(s) glue(LnSWoUB, s) 294#define LnSWoUB(s) glue(LnSWoUB, s)
236#define MLnS(s) glue(MLnS, s) 295#define MLnS(s) glue(MLnS, s)
237#define LdnStM(s) glue(LdnStM, s) 296#define LdnStM(s) glue(LdnStM, s)
@@ -1108,9 +1167,9 @@ struct pkh_inst {
1108typedef arm_inst * ARM_INST_PTR; 1167typedef arm_inst * ARM_INST_PTR;
1109 1168
1110#define CACHE_BUFFER_SIZE (64 * 1024 * 2000) 1169#define CACHE_BUFFER_SIZE (64 * 1024 * 2000)
1111char inst_buf[CACHE_BUFFER_SIZE]; 1170static char inst_buf[CACHE_BUFFER_SIZE];
1112int top = 0; 1171static int top = 0;
1113inline void *AllocBuffer(unsigned int size) { 1172static inline void *AllocBuffer(unsigned int size) {
1114 int start = top; 1173 int start = top;
1115 top += size; 1174 top += size;
1116 if (top > CACHE_BUFFER_SIZE) { 1175 if (top > CACHE_BUFFER_SIZE) {
@@ -1120,67 +1179,6 @@ inline void *AllocBuffer(unsigned int size) {
1120 return (void *)&inst_buf[start]; 1179 return (void *)&inst_buf[start];
1121} 1180}
1122 1181
1123int CondPassed(ARMul_State* cpu, unsigned int cond) {
1124 #define NFLAG cpu->NFlag
1125 #define ZFLAG cpu->ZFlag
1126 #define CFLAG cpu->CFlag
1127 #define VFLAG cpu->VFlag
1128
1129 int temp = 0;
1130
1131 switch (cond) {
1132 case 0x0:
1133 temp = ZFLAG;
1134 break;
1135 case 0x1: // NE
1136 temp = !ZFLAG;
1137 break;
1138 case 0x6: // VS
1139 temp = VFLAG;
1140 break;
1141 case 0x7: // VC
1142 temp = !VFLAG;
1143 break;
1144 case 0x4: // MI
1145 temp = NFLAG;
1146 break;
1147 case 0x5: // PL
1148 temp = !NFLAG;
1149 break;
1150 case 0x2: // CS
1151 temp = CFLAG;
1152 break;
1153 case 0x3: // CC
1154 temp = !CFLAG;
1155 break;
1156 case 0x8: // HI
1157 temp = (CFLAG && !ZFLAG);
1158 break;
1159 case 0x9: // LS
1160 temp = (!CFLAG || ZFLAG);
1161 break;
1162 case 0xa: // GE
1163 temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
1164 break;
1165 case 0xb: // LT
1166 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
1167 break;
1168 case 0xc: // GT
1169 temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG));
1170 break;
1171 case 0xd: // LE
1172 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
1173 break;
1174 case 0xe: // AL
1175 temp = 1;
1176 break;
1177 case 0xf:
1178 temp = 1;
1179 break;
1180 }
1181 return temp;
1182}
1183
1184enum DECODE_STATUS { 1182enum DECODE_STATUS {
1185 DECODE_SUCCESS, 1183 DECODE_SUCCESS,
1186 DECODE_FAILURE 1184 DECODE_FAILURE
HIC SVNT DRACONES