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authorGravatar Lioncash2015-08-25 23:52:35 -0400
committerGravatar Lioncash2015-08-25 23:59:01 -0400
commit01dd833ffa6483b868c848dca7cf30769859587c (patch)
tree1b0f8b97a9b183ac5606201f9b54ee25f0d4c8d4 /src
parentMerge pull request #1073 from lioncash/guard (diff)
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dyncom: Change return type of CondPassed to bool
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp96
1 files changed, 39 insertions, 57 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 01c712f24..0756cfe61 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -49,65 +49,47 @@ enum {
49 49
50typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper); 50typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
51 51
52static int CondPassed(ARMul_State* cpu, unsigned int cond) { 52static bool CondPassed(ARMul_State* cpu, unsigned int cond) {
53 const u32 NFLAG = cpu->NFlag; 53 const bool n_flag = cpu->NFlag != 0;
54 const u32 ZFLAG = cpu->ZFlag; 54 const bool z_flag = cpu->ZFlag != 0;
55 const u32 CFLAG = cpu->CFlag; 55 const bool c_flag = cpu->CFlag != 0;
56 const u32 VFLAG = cpu->VFlag; 56 const bool v_flag = cpu->VFlag != 0;
57
58 int temp = 0;
59 57
60 switch (cond) { 58 switch (cond) {
61 case 0x0: 59 case ConditionCode::EQ:
62 temp = ZFLAG; 60 return z_flag;
63 break; 61 case ConditionCode::NE:
64 case 0x1: // NE 62 return !z_flag;
65 temp = !ZFLAG; 63 case ConditionCode::CS:
66 break; 64 return c_flag;
67 case 0x2: // CS 65 case ConditionCode::CC:
68 temp = CFLAG; 66 return !c_flag;
69 break; 67 case ConditionCode::MI:
70 case 0x3: // CC 68 return n_flag;
71 temp = !CFLAG; 69 case ConditionCode::PL:
72 break; 70 return !n_flag;
73 case 0x4: // MI 71 case ConditionCode::VS:
74 temp = NFLAG; 72 return v_flag;
75 break; 73 case ConditionCode::VC:
76 case 0x5: // PL 74 return !v_flag;
77 temp = !NFLAG; 75 case ConditionCode::HI:
78 break; 76 return (c_flag && !z_flag);
79 case 0x6: // VS 77 case ConditionCode::LS:
80 temp = VFLAG; 78 return (!c_flag || z_flag);
81 break; 79 case ConditionCode::GE:
82 case 0x7: // VC 80 return ((!n_flag && !v_flag) || (n_flag && v_flag));
83 temp = !VFLAG; 81 case ConditionCode::LT:
84 break; 82 return ((n_flag && !v_flag) || (!n_flag && v_flag));
85 case 0x8: // HI 83 case ConditionCode::GT:
86 temp = (CFLAG && !ZFLAG); 84 return ((!n_flag && !v_flag && !z_flag) || (n_flag && v_flag && !z_flag));
87 break; 85 case ConditionCode::LE:
88 case 0x9: // LS 86 return ((n_flag && !v_flag) || (!n_flag && v_flag)) || z_flag;
89 temp = (!CFLAG || ZFLAG); 87 case ConditionCode::AL:
90 break; 88 case ConditionCode::NV: // Unconditional
91 case 0xa: // GE 89 return true;
92 temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG)); 90 }
93 break; 91
94 case 0xb: // LT 92 return false;
95 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
96 break;
97 case 0xc: // GT
98 temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG));
99 break;
100 case 0xd: // LE
101 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
102 break;
103 case 0xe: // AL
104 temp = 1;
105 break;
106 case 0xf:
107 temp = 1;
108 break;
109 }
110 return temp;
111} 93}
112 94
113static unsigned int DPO(Immediate)(ARMul_State* cpu, unsigned int sht_oper) { 95static unsigned int DPO(Immediate)(ARMul_State* cpu, unsigned int sht_oper) {
HIC SVNT DRACONES