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authorGravatar Lioncash2015-02-16 01:02:59 -0500
committerGravatar Lioncash2015-02-16 01:03:01 -0500
commit012d1e32ad9dc772d2234efcd18fdb1fae9d14b3 (patch)
tree73bbb46892f26e8f348753b0512a1f527aba1c8e /src
parentMerge pull request #539 from linkmauve/framebuffer-formats (diff)
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dyncom: Actually set the destination register for USAD8/USADA8.
Idiotville: Population: 1 - Inhabitant name: Lioncash
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index f4b3c4734..a8b3c1276 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3211,6 +3211,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index)
3211 3211
3212 inst_cream->op1 = BITS(inst, 20, 24); 3212 inst_cream->op1 = BITS(inst, 20, 24);
3213 inst_cream->op2 = BITS(inst, 5, 7); 3213 inst_cream->op2 = BITS(inst, 5, 7);
3214 inst_cream->Rd = BITS(inst, 16, 19);
3214 inst_cream->Rm = BITS(inst, 8, 11); 3215 inst_cream->Rm = BITS(inst, 8, 11);
3215 inst_cream->Rn = BITS(inst, 0, 3); 3216 inst_cream->Rn = BITS(inst, 0, 3);
3216 inst_cream->Ra = BITS(inst, 12, 15); 3217 inst_cream->Ra = BITS(inst, 12, 15);