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authorGravatar ReinUsesLisp2020-04-06 00:54:22 -0300
committerGravatar ReinUsesLisp2020-04-06 00:54:22 -0300
commit79970c9174794c621dd3b0e5cfde8a10138518c0 (patch)
tree14873014f9744d9b77b219e1fd0e6867d22d710e /src
parentMerge pull request #3579 from Kewlan/reorder-shoulder (diff)
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shader/memory: Minor fixes in ATOM
Diffstat (limited to '')
-rw-r--r--src/video_core/shader/decode/memory.cpp62
1 files changed, 30 insertions, 32 deletions
diff --git a/src/video_core/shader/decode/memory.cpp b/src/video_core/shader/decode/memory.cpp
index b8f63922f..20a953379 100644
--- a/src/video_core/shader/decode/memory.cpp
+++ b/src/video_core/shader/decode/memory.cpp
@@ -27,29 +27,26 @@ using Tegra::Shader::StoreType;
27 27
28namespace { 28namespace {
29 29
30Node GetAtomOperation(AtomicOp op, bool is_signed, Node memory, Node data) { 30OperationCode GetAtomOperation(AtomicOp op) {
31 const OperationCode operation_code = [op] { 31 switch (op) {
32 switch (op) { 32 case AtomicOp::Add:
33 case AtomicOp::Add: 33 return OperationCode::AtomicIAdd;
34 return OperationCode::AtomicIAdd; 34 case AtomicOp::Min:
35 case AtomicOp::Min: 35 return OperationCode::AtomicIMin;
36 return OperationCode::AtomicIMin; 36 case AtomicOp::Max:
37 case AtomicOp::Max: 37 return OperationCode::AtomicIMax;
38 return OperationCode::AtomicIMax; 38 case AtomicOp::And:
39 case AtomicOp::And: 39 return OperationCode::AtomicIAnd;
40 return OperationCode::AtomicIAnd; 40 case AtomicOp::Or:
41 case AtomicOp::Or: 41 return OperationCode::AtomicIOr;
42 return OperationCode::AtomicIOr; 42 case AtomicOp::Xor:
43 case AtomicOp::Xor: 43 return OperationCode::AtomicIXor;
44 return OperationCode::AtomicIXor; 44 case AtomicOp::Exch:
45 case AtomicOp::Exch: 45 return OperationCode::AtomicIExchange;
46 return OperationCode::AtomicIExchange; 46 default:
47 default: 47 UNIMPLEMENTED_MSG("op={}", static_cast<int>(op));
48 UNIMPLEMENTED_MSG("op={}", static_cast<int>(op)); 48 return OperationCode::AtomicIAdd;
49 return OperationCode::AtomicIAdd; 49 }
50 }
51 }();
52 return SignedOperation(operation_code, is_signed, std::move(memory), std::move(data));
53} 50}
54 51
55bool IsUnaligned(Tegra::Shader::UniformType uniform_type) { 52bool IsUnaligned(Tegra::Shader::UniformType uniform_type) {
@@ -392,7 +389,9 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
392 instr.atom.operation == AtomicOp::SafeAdd, 389 instr.atom.operation == AtomicOp::SafeAdd,
393 "operation={}", static_cast<int>(instr.atom.operation.Value())); 390 "operation={}", static_cast<int>(instr.atom.operation.Value()));
394 UNIMPLEMENTED_IF_MSG(instr.atom.type == GlobalAtomicType::S64 || 391 UNIMPLEMENTED_IF_MSG(instr.atom.type == GlobalAtomicType::S64 ||
395 instr.atom.type == GlobalAtomicType::U64, 392 instr.atom.type == GlobalAtomicType::U64 ||
393 instr.atom.type == GlobalAtomicType::F16x2_FTZ_RN ||
394 instr.atom.type == GlobalAtomicType::F32_FTZ_RN,
396 "type={}", static_cast<int>(instr.atom.type.Value())); 395 "type={}", static_cast<int>(instr.atom.type.Value()));
397 396
398 const auto [real_address, base_address, descriptor] = 397 const auto [real_address, base_address, descriptor] =
@@ -403,11 +402,11 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
403 } 402 }
404 403
405 const bool is_signed = 404 const bool is_signed =
406 instr.atoms.type == AtomicType::S32 || instr.atoms.type == AtomicType::S64; 405 instr.atom.type == GlobalAtomicType::S32 || instr.atom.type == GlobalAtomicType::S64;
407 Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor); 406 Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
408 Node value = GetAtomOperation(static_cast<AtomicOp>(instr.atom.operation), is_signed, gmem, 407 SetRegister(bb, instr.gpr0,
409 GetRegister(instr.gpr20)); 408 SignedOperation(GetAtomOperation(instr.atom.operation), is_signed, gmem,
410 SetRegister(bb, instr.gpr0, std::move(value)); 409 GetRegister(instr.gpr20)));
411 break; 410 break;
412 } 411 }
413 case OpCode::Id::ATOMS: { 412 case OpCode::Id::ATOMS: {
@@ -422,10 +421,9 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
422 const s32 offset = instr.atoms.GetImmediateOffset(); 421 const s32 offset = instr.atoms.GetImmediateOffset();
423 Node address = GetRegister(instr.gpr8); 422 Node address = GetRegister(instr.gpr8);
424 address = Operation(OperationCode::IAdd, std::move(address), Immediate(offset)); 423 address = Operation(OperationCode::IAdd, std::move(address), Immediate(offset));
425 Node value = 424 SetRegister(bb, instr.gpr0,
426 GetAtomOperation(static_cast<AtomicOp>(instr.atoms.operation), is_signed, 425 SignedOperation(GetAtomOperation(instr.atoms.operation), is_signed,
427 GetSharedMemory(std::move(address)), GetRegister(instr.gpr20)); 426 GetSharedMemory(std::move(address)), GetRegister(instr.gpr20)));
428 SetRegister(bb, instr.gpr0, std::move(value));
429 break; 427 break;
430 } 428 }
431 case OpCode::Id::AL2P: { 429 case OpCode::Id::AL2P: {